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| preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. no v e mb er 2 010 d o c id 158 18 re v 5 1 /1 47 1 stm32f205xx stm32f207xx arm-based 32-bit mcu , 150dmips , up to 1 mb flash/128+4kb ram, usb o t g hs/fs , ether net, 17 tims , 3 adcs , 15 comm. interf aces & camer a features core: arm 32-bit co rt ex ?- m3 c p u w i th ad ap tiv e re al- t im e ac ce ler a t o r (a rt acc e lerator? ) allowing 0-wait s t ate exec ution pe rf or man ce f r o m fla s h mem o r y , f r e que ncy up t o 120 mhz, memo ry pr ot ecti on un it, 15 0 d m i ps/ 1. 25 dmi ps/ mhz (dh r yst o ne 2. 1) me mor i es ? u p t o 1 m b yt e of flash me mor y ? u p to 12 8 + 4 k b yte s of sram ? f le xib l e static memor y controller that suppor ts compact flash, sram, psram, n o r and nan d memor i es ? l cd p a r a llel int e r f a c e , 808 0/ 68 00 mo de s clock, re se t a nd sup p ly m ana gem ent ? 1 . 8 t o 3. 6 v a ppli c a t io n su pp ly an d i / o s ? p or, pdr , pvd and bor ? 4 to 26 mhz cr y stal oscillator ? i nt er na l 1 6 m h z f a c t o r y- tr im m e d r c ( 1 % acc u r a cy) ? 3 2 khz oscillator f o r r t c with c a libr a tion ? i nter nal 32 khz rc with c a libr a tion lo w po wer ? s leep , st op an d sta n d b y mod e s ?v ba t sup p ly f o r r t c , 20 32 bit bac k u p re giste r s , an d opt io nal 4 kb bac kup sram 3 12 -b it, 0. 5 s a/d co nv er te rs ? up t o 24 cha n n e ls ? up to 6 msps in tr iple inter l ea v e d mode 2 1 2 - b it d/ a co nver te rs ge ner al- pu r p ose dm a ? 1 6 - st re am d m a co nt ro ller wit h ce ntr a liz ed fi fos and b u rst sup por t up t o 17 tim e rs ? u p t o t w e l v e 16- bit an d tw o 32 -bit ti mer s , each wit h up t o 4 i c / o c / p wm or pu lse co un te r an d qua dr a t u r e ( i ncr e me nt al) enco der inpu t debu g mod e ? s er ial wire deb ug (swd) & jt a g interf aces ? c o r te x- m3 emb ed ded t r ace ma cr ocell ? 1. package not in producti on (for developme n t only). up to 140 i/o ports with interrupt capability: ? u p to 1 36 f a st i / o s up t o 60 mhz ? u p to 1 38 5 v - t oler ant i/ o s up to 1 5 co m m u n i ca tion in te rf ac es ? u p to 3 i 2 c int e r f aces ( s mbus/ p mbus) ? u p to 4 usar ts a nd 2 u a r t s (7 .5 m b it /s , i s o 78 16 in te rf ac e , l i n, ir d a , m o de m co nt ro l ) ? u p t o 3 spis (3 0 mb it/ s), 2 wit h m u x e d i 2 s t o a ch i e v e au dio c l as s a ccu r a c y v i a au dio pll o r e xt e r n al pll ? 2 can interf aces (2.0b activ e ) ? s di o in te rf ac e advan c e d conn ect i vit y ? u sb 2. 0 f u ll- sp ee d de vice/ h o s t / o tg co nt ro ller wit h on -chip phy ? u sb 2. 0 h i gh- spee d/ fu ll-spe e d d e v i ce /h ost / o t g co nt ro ller wit h de dic a t e d dma, on -chip f u ll-spe ed phy a nd ulpi ? 1 0 / 1 00 et he r n et ma c wit h d ed i ca te d dma: s u p p o r ts iee e 1 5 8 8 v 2 ha rd w a r e , mi i/r mi i 8- to 14-bit parallel ca me r a in te rf ac e: u p t o 27 m b yte / s at 27 mhz o r 48 m b yte / s at 48 mhz crc calculat io n unit , 9 6 - b it uniq ue i d ana l og t r u e ra ndo m nu mbe r ge ner at or t ab l e 1. de vi ce s u mmary re f e re nc e p a r t n u mber s t m3 2f205xx stm32f20 5rb , s t m 3 2f205 r c , stm32f20 5re, stm32f20 5rf , s t m3 2f205rg , stm32 f 2 05vb , stm32f20 5vc , stm32f2 05ve , stm32f20 5vf stm32f20 5v g, stm32f205 z c , stm32 f 205ze, stm32f20 5zf , s t m3 2f205zg s t m3 2f207xx stm32f20 7i c , stm3 2f207i e, s t m32f207 if , stm32f20 7i g, stm3 2f 207zc , stm32f20 7ze, stm32f20 7zf , s t m3 2f207zg , stm32f2 07vc , stm32f20 7ve , stm32f20 7vf , stm32f20 7v g lqfp64 (10 10 mm) lqfp100 (14 14 mm) lqfp144 (20 20 mm) lqfp176 (24 24 mm)( 1) fbga uf b g a 1 7 6 (10 10 mm) wl c s p64 + 2 (0. 400 mm pit c h ) fbga www.st.com http://
contents stm32f205xx, stm32f207xx 2/147 doc id 15818 rev 5 contents 1 i ntr oduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 d esc ription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2. 1 f ull compatibility through out the f a mily . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2. 2 d e v ice o v er vie w . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2. 2. 1 a rm ? co r t e x ? - m 3 co re wit h e m b e d d e d flas h an d sram . . . . . . . . . 1 6 2 .2 .2 m em o r y pr o te ctio n un it . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 2 . 2 . 3 a d a p t iv e r e a l - t im e m e m o r y a cc e le r a to r (ar t acc e le r a to r ? ) . . . . . . . . 1 6 2 .2 .4 e m b ed de d flas h me m o r y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 6 2 . 2 . 5 c r c ( cyclic r e d u n d a n cy ch ec k ) c a lc ula t io n un it . . . . . . . . . . . . . . . . . . 1 7 2 .2 .6 t r u e r a nd o m n u m b er g e n e r a to r (rn g) . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 2 . 2 . 7 e m b ed de d sram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 2 . 2 . 8 m ult i -ah b b u s m a tr ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 2 .2 .9 d m a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 8 2 . 2 . 1 0 fsm c ( f le xib l e st at ic m e mo r y co n t ro lle r) . . . . . . . . . . . . . . . . . . . . . . . . 1 8 2 . 2 . 1 1 ne st ed v e cto r ed in te rr u p t co nt ro ller ( n vic ) . . . . . . . . . . . . . . . . . . . . . . 1 9 2 . 2 . 1 2 ext e r n al inte r r u p t/e v e nt co nt ro ller ( exti) . . . . . . . . . . . . . . . . . . . . . . . 1 9 2 . 2 . 1 3 clo c ks an d st ar t u p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 9 2 .2 .1 4 b o ot m o d e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 2 .2 .1 5 p o wer su pp ly sch em e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 2 .2 .1 6 p o wer su pp ly su pe r v isor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 2 . 2 . 1 7 v o lt ag e re g u la to r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 0 2. 2. 18 real- t ime cloc k (r tc), bac ku p sram an d ba c k u p re gist ers . . . . . . . . 23 2 .2 .1 9 l o w- po wer m o de s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 2. 2. 20 v ba t op e r a tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 2 . 2 . 2 1 tim e r s a n d w a tch d o g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 2 . 2 . 2 2 ba sic tim e r s tim 6 a n d tim 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2 . 2 . 2 3 in d e p e n d e n t w a tc hd og . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2 . 2 . 2 4 win d o w w a tch d o g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 6 2 . 2 . 2 5 sys t ic k tim e r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 2 .2 .2 6 i2 c b u s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 2. 2. 27 univ er sal synch r on ou s/ asynchr o n ous re ce iv er t r an smit te rs (u ar ts /usar ts ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 2 . 2 . 2 8 se r i al pe r i ph e r a l in te rf ac e (spi ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 stm32f205xx, stm32f207xx contents doc id 15818 rev 5 3/147 2. 2. 29 int e r - in te g r at ed sou n d ( i 2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 2 . 2 . 3 0 sdi o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 2. 2. 31 et her net ma c in te rf ace wit h ded icat ed dma and i eee 158 8 su pp or t . 29 2 . 2 . 3 2 co n t ro lle r a r e a n e two r k ( c an) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 2 . 2 . 3 3 un iv e r sa l s e r i a l b u s on -t he -g o fu ll-s p e e d ( o tg_ f s) . . . . . . . . . . . . . . . 2 9 2. 2. 34 univ er sal se r i al b u s o n - t h e - go hi gh- spee d (o t g _hs) . . . . . . . . . . . . . 30 2 . 2 . 3 5 a u dio pl l ( p ll i2 s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 0 2 . 2 . 3 6 dig ita l ca m e r a in te rf a ce ( dcm i) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 2 .2 .3 7 g p io s ( g e n e r a l-p u r p o se in pu ts /o ut pu ts) . . . . . . . . . . . . . . . . . . . . . . . . 3 1 2 . 2 . 3 8 adc s ( a n a l og -t o- dig i ta l co n v e r t e r s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1 2 .2 .3 9 d a c ( d ig ita l -t o- an a l og co n v er t e r ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2 .2 .4 0 t e m p er a tu r e se n so r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2 . 2 . 4 1 se r i al wire j t a g d e b u g p o r t ( s wj -dp) . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 2 . 2 . 4 2 em b e d d e d t r ace m a cr oce ll? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 3 p inouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4 m emor y ma ppin g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5 e lectrical c h aracteristi cs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5. 1 p ar ameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 5 . 1 . 1 m inim u m a n d m a xim u m v a lue s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5 . 1 . 2 t yp ica l v a lue s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5 . 1 . 3 t yp ica l cu r v e s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5 .1 .4 l oa d i n g ca p a cit o r . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5 . 1 . 5 p in in pu t v o lt ag e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 5 .1 .6 p o w er su pp ly sch em e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5 . 1 . 7 c u r r e n t co ns um p t ion m e as ur em e n t . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 5. 2 a bsolute maxim u m r a tings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5. 3 o per a ting conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 5 .3 .1 g en er a l o p e r at ing c o n d it ion s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 5 . 3 . 2 o pe r a t i ng co n d it ion s a t po we r- up / po we r- do w n (r e g u l at or n o t b y pa sse d ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 5 . 3 . 3 o pe r a t i ng co n d it ion s a t po we r- up / po we r- do w n in r e gu lat o r b y pa ss m o d e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 5 . 3 . 4 e m b ed de d re se t an d po we r c o n t r o l b l o c k ch a r a ct e r i s t ics . . . . . . . . . . . 6 0 5 .3 .5 s u p p l y cur r e n t c h a r ac ter i s tics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1 5 . 3 . 6 e xt er n a l cloc k so u r ce ch a r act e r i s t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 cont ent s stm32f205xx, stm32f207xx 4/147 doc id 15818 rev 5 5 . 3 . 7 i n t e r na l clo c k sou r ce ch ar a c te r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 5 . 3 . 8 w ak e u p t i me f r o m lo w- po we r m o de . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 5 . 3 . 9 p l l ch ar a cte r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 5. 3. 10 pll spr e a d sp ect r um cloc k gen er a t io n (sscg) ch ar act e r i st ics . . . . . . 73 5 . 3 . 1 1 m e m o r y ch ar a cte r i st ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 5 . 3 . 1 2 em c c h a r ac te r i stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 5 . 3 . 1 3 ab so lut e ma xim u m r a t i ng s (e lect r i ca l se ns itivit y) . . . . . . . . . . . . . . . . . 7 7 5 . 3 . 1 4 i/ o po r t cha r a cte r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 5 . 3 . 1 5 nr st pin c h a r ac ter i s t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 5 . 3 . 1 6 tim t i m e r ch ar a cte r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 5 . 3 . 1 7 co m m un ica t io ns in te rf a ce s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 5 . 3 . 1 8 1 2 - b it adc ch ar a cte r i st ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 5 . 3 . 1 9 d a c e l e ctr ica l s p e cific at ion s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 2 5 .3 .2 0 t e m p er a tu r e se n so r c h a r ac te r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 5. 3. 21 v ba t mo n i to r i ng ch a r a ct e r i st ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 5 . 3 . 2 2 em b e d d e d re f e re n ce v o lta g e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 5 . 3 . 2 3 fsm c c h a r ac ter i s t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 5 5 . 3 . 2 4 ca m e r a in te rf a ce ( dcm i) tim i n g sp ecif ica t io n s . . . . . . . . . . . . . . . . . . 1 2 3 5 . 3 . 2 5 sd/ s dio m m c c a r d ho st int e r f a ce ( s dio ) ch ar a cte r i stic s . . . . . . . . . 1 2 4 5 . 3 . 2 6 r t c ch ar a cte r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 5 6 p ac ka g e c haracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6. 1 p ac kage mech anical d a ta . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 6. 2 t her mal char acter i stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 7 p ar t n u mbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 appendix a a pplication b l oc k dia g rams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 a.1 m ain app lications v e rsus pac kage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 a.2 a pplication e x ample with regulator off . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 a.3 u sb o t g full sp eed ( f s) interf ace solutio n s . . . . . . . . . . . . . . . . . . . . . 137 a.4 u sb o t g hig h sp eed (hs) in terf a c e solu tions . . . . . . . . . . . . . . . . . . . . 138 a.5 c omplete audio pla y er solutions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 stm32f205xx, stm32f207xx list of tables doc id 15818 rev 5 5/147 list of tab l es tab l e 1. de vice su m m a r y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 tab l e 2. stm3 2 f 2 0 5 x x a n d stm 3 2f2 0 7 xx fe at ur es a n d p e r i ph e r a l co u n t s . . . . . . . . . . . . . . . . . . 1 1 tab l e 3. time r fe at ur e com p ar iso n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 tab l e 4. usar t fe atu r e c o m p ar iso n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 7 tab l e 5. stm3 2 f 2 0 x p i n an d b a ll d e f in itio ns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 tab l e 6. alte rn at e fu nc tion m a pp in g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 8 tab l e 7. volt ag e ch ar a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 tab l e 8. cu rr en t c h a r a ct e r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6 tab l e 9. the r m a l ch ar a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 tab l e 10 . ge n e r a l op er a ting c o n d i tion s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 tab l e 11 . l im ita t io n s d e p e n d i ng o n th e op e r a t in g po we r sup p l y r a n g e . . . . . . . . . . . . . . . . . . . . . . . 5 8 ta ble 1 2 . o per at ing co ndit i on s a t po we r- up / powe r - down ( r e gula t o r no t b y p a ssed) . . . . . . . . . . . . 59 ta ble 1 3 . o per at ing co ndit i on s a t po we r- up / powe r - down in r e g u lat o r by pa ss m o d e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 tab l e 14 . e m b e d d e d re se t a n d p o w e r c o n t r o l blo ck ch ar ac te rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . 6 0 t a b l e 15 . t ypic al an d m a xim u m c u rr en t co nsu m pt ion in ru n m o d e , c o d e with d a t a pr oc es sing r u nn in g fro m flas h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 t a b l e 16 . t ypic al an d m a xim u m cu rr en t co nsu m pt ion in ru n m o d e , c o d e with d a t a pr oc es sing r u n n in g fr om r a m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 tab l e 17 . t ypic al an d m a xim u m cu rr en t co nsu m pt ion in sle e p m o de . . . . . . . . . . . . . . . . . . . . . . . . 6 3 tab l e 18 . t ypic al an d m a xim u m cu rr en t co nsu m pt ion s in s to p m o de . . . . . . . . . . . . . . . . . . . . . . . . 6 4 tab l e 19 . t ypic al an d m a xim u m cu rr en t co nsu m pt ion s in sta n d b y m o d e . . . . . . . . . . . . . . . . . . . . . 6 4 tab l e 20 . t ypic al an d m a xim u m cu rr en t co nsu m pt ion s in v bat mod e . . . . . . . . . . . . . . . . . . . . . . . 6 5 tab l e 21 . p er ip he ra l cu r r e n t co ns um p t io n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 tab l e 22 . hig h- sp ee d ex te rn al us er clo ck ch ar ac te rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 tab l e 23 . l o w - sp e e d ex te rn al us er clo ck ch ar ac te rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 table 24. hse 4-26 mhz os cillator c h aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 9 table 25. l se oscillator c h aracteristic s (f lse = 32 .7 6 8 k h z) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 0 table 26. h si os cillator c h aracteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 table 27. l si oscillator characteristic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1 tab l e 28 . l o w - p o w e r mo d e wak e u p tim i n g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 tab l e 29 . m ain pl l c h ar ac te rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 tab l e 30 . p ll i2 s ( a ud io pll ) c h ar ac te rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 tab l e 31 . sscg p a r a m e te rs co ns tra i n t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 tab l e 32 . f lash m e m o r y ch a r a cte r i s t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 tab l e 33 . f lash m e m o r y p r o g r a m m i n g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 ta ble 3 4 . f la sh memo ry pr ogr am ming wit h v pp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 5 tab l e 35 . f lash m e m o r y e n d u r a n c e an d da ta r e t e n tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 tab l e 36 . e m s ch a r a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 tab l e 37 . e m i c h a r a cte r i stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7 tab l e 38 . esd ab so lut e ma xim u m ra tin g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 tab l e 39 . e lec t r i cal se ns itivitie s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 tab l e 40 . i/o s t a t ic c h a r a ct e r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 8 tab l e 41 . o u t p u t vo lta g e cha r act e r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 tab l e 42 . i/o ac ch a r a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 0 tab l e 43 . nrst pin ch a r a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 tab l e 44 . c h a r a c t e r ist i cs of tim x co n n e ct e d to t h e apb 1 d o m a i n . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 tab l e 45 . c h a r a c t e r ist i cs of tim x co n n e ct e d to t h e apb 2 d o m a i n . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 list of tables stm32f205xx, stm32f207xx 6/147 doc id 15818 rev 5 t ab l e 46 . i 2 c ch ar ac te rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 5 ta ble 4 7 . s cl f r e que ncy ( f pclk1 = 30 mhz., v dd = 3 . 3 v) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 tab l e 48 . spi ch ar ac ter i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 t ab l e 49 . i 2 s cha r ac ter i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 tab l e 50 . u sb otg fs st ar tu p tim e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 tab l e 51 . u sb otg fs dc e l ect r ica l c h a r a ct e r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 tab l e 52 . u sb otg fs e l ec tric al cha r act e r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 tab l e 53 . clo ck tim i ng p a r a m e te rs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 tab l e 54 . u l p i t i min g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 tab l e 55 . e th er n e t dc ele ctr ica l ch a r a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 tab l e 56 . d yn a m ic s ch a r a cte r i s t ics : et he rn e t m a c sig n a l s f o r sm i . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 tab l e 57 . d yn a m ic s ch a r a cte r i s t ics : et he rn e t m a c sig n a l s f o r rm ii . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 tab l e 58 . d yn a m ic s ch a r a cte r i s t ics : et he rn e t m a c sig n a l s f o r m i i . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 tab l e 59 . a d c ch ar ac te rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 tab l e 60 . a dc ac cu ra cy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 9 tab l e 61 . d ac ch ar ac te rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 2 tab l e 62 . t s ch ar a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 t ab l e 63 . v bat m o nit o r i ng cha r a ct e r i stics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 tab l e 64 . e m b e d d e d int e r n a l r e f e r e n ce vo lta g e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 4 tab l e 65 . a syn ch ro n o u s no n- m u lt iple xe d sram /psr am /no r r e a d tim i n g s . . . . . . . . . . . . . . . . . 1 0 6 tab l e 66 . a syn ch ro n o u s no n- m u lt iple xe d sram /psr am /no r w r ite t i min g s . . . . . . . . . . . . . . . . . 1 0 7 tab l e 67 . a syn ch ro n o u s mu ltip lex e d psr am /no r r e a d tim i n g s . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 8 tab l e 68 . a syn ch ro n o u s mu ltip lex e d psr am /no r w r ite t i min g s . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 9 tab l e 69 . s yn ch ro no u s m u ltip le xe d no r/p s ram r e a d tim i ng s . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 1 tab l e 70 . s yn ch ro no u s m u ltip le xe d psra m writ e tim i ng s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 3 tab l e 71 . s yn ch ro no u s n o n - mu ltip lex e d n o r/ psram r e ad tim i n g s . . . . . . . . . . . . . . . . . . . . . . . . 1 1 4 tab l e 72 . s yn ch ro no u s n o n - mu ltip lex e d ps ram wr ite tim i n g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 5 tab l e 73 . s witc h in g ch ar ac te rist ics fo r pc ca rd /c f re ad a n d writ e c ycle s . . . . . . . . . . . . . . . . . . . 1 2 0 tab l e 74 . s witc h in g ch ar ac te rist ics fo r n a nd fla sh r e a d an d wr ite cy cles . . . . . . . . . . . . . . . . . . . 1 2 3 tab l e 75 . dcm i ch ar ac te rist ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 3 tab l e 76 . s d / m m c ch a r a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4 tab l e 77 . r tc c h a r a ct e r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 5 ta ble 7 8 . l qfp6 4 ? 10 x 1 0 mm 64 pin low- pr of ile qu ad f l at p a ckage m e cha n ical da ta . . . . . . . . . 127 ta ble 7 9 . w lcsp64 + 2 - 0. 400 mm pit ch wa fe r level chip size pa ckag e mech anical d a t a . . . . . . . 128 t a b l e 80 . l q p f 1 0 0 ? 1 4 x 1 4 mm 10 0- pin lo w- pr of ile qu ad f l at p a ck ag e m e c h a n ic al da ta . . . . . . . 1 2 9 ta ble 8 1 . l qfp1 44, 20 x 2 0 mm, 14 4-p i n low- pr of ile qua d f l at p a ckage m e chan ical dat a . . . . . . . 130 t a b l e 82 . l q f p17 6 - lo w pr of ile qu ad f l at pa ck ag e 24 2 4 1 . 4 m m pa ck ag e m e c h a n ic al da ta . 1 3 1 t a b l e 83 . u f b g a 17 6+ 25 - u l tra t h in f i ne p i tch b a ll gr id ar ra y 10 10 0. 6 mm me ch an ica l d a t a . 1 3 2 tab l e 84 . p ac ka ge t h e r m a l ch ar a cte ris t ics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 tab l e 85 . or d e r ing in fo rm at ion s ch e m e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 tab l e 86 . m ain a p p lica t io ns ve rs us pa ck ag e fo r stm 3 2f2 0 7 xx m i cro co n t ro lle rs . . . . . . . . . . . . . . 1 3 5 tab l e 87 . d o cu m e n t r e v i sion h i st or y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 3 stm32f205xx, stm32f207xx list of figures doc id 15818 rev 5 7/147 list of figures figu re 1 . co mp a t ib le b o a r d de sig n : l q fp1 4 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 figu re 2 . co mp a t ib le b o a r d de sig n : l q fp1 0 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figu re 3 . co mp a t ib le b o a r d de sig n : l q fp6 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 figu re 4 . stm3 2 f 2 0 x b l oc k d i a g r a m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 5 figu re 5 . m u lti- ahb ma tr ix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 7 fig u r e 6. st ar tu p in re gu lat o r b y p a ss/r e g u lat o r of f mo de: slow v dd slo pe - po we r- do wn r e se t rise n a fte r v cap_1 /v ca p _ 2 stabiliz ation . . . . . . . . . . . . . . . . . . . . . . . . 22 fig u r e 7. st ar tu p in re gu lat o r b y p a ss/r e g u lat o r of f mo de: slow v dd slo pe - po we r- do wn r e se t rise n b e f o r e v cap_1 /v cap_2 s t abiliz ation . . . . . . . . . . . . . . . . . . . . . . 22 figu re 8 . sar tu p in re gu la to r b yp a ss/r e gu lat o r o ff an d int e r n a l r e s e t o ff . . . . . . . . . . . . . . . . . . . . . . 2 2 figu re 9 . stm3 2 f 2 0 x l q fp6 4 p i no u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figu re 1 0 . s tm3 2 f 2 0 x w l cs p6 4 + 2 ballo u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 figu re 1 1 . s tm3 2 f 2 0 x l q fp1 0 0 pin o u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figu re 1 2 . s tm3 2 f 2 0 x l q fp1 4 4 pin o u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figu re 1 3 . s tm3 2 f 2 0 x l q fp1 7 6 pin o u t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figu re 1 4 . s tm3 2 f 2 1 xxx ufbg a17 6 b a llo ut . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 figu re 1 5 . m em o r y ma p . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 figu re 1 6 . p in loa d i ng co n d it ion s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 figu re 1 7 . p in inp u t v o lta g e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 figu re 1 8 . p ow er su p p ly sch e m e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 figu re 1 9 . c u r r e n t c o n su m pt ion m e asu r em e n t sch e m e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5 fig u r e 20 . n um ber of wait sta t e s ver s u s f cpu and v dd ra ng e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 9 figu re 2 1 . hig h- sp ee d ex te rn al clo ck s o u r c e ac t i min g d i ag ra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 figu re 2 2 . l o w - sp e e d ex te rn al clo ck s o u r c e ac t i min g d i ag ra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 figu re 2 3 . t ypic al ap plic at ion wit h an 8 m h z cr ysta l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 figu re 2 4 . t ypic al ap plic at ion wit h a 32 .7 68 k h z cry sta l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 0 figu re 2 5 . p ll ou tp ut clo ck wa vef o r m s in ce n t e r s p r e a d m o d e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 figu re 2 6 . p ll ou tp ut clo ck wa vef o r m s in d o w n spr e ad m o d e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 4 figu re 2 7 . i/o ac ch a r a cte ris t ics de fin i tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 figu re 2 8 . r e co m m e nd e d n r st p i n pr ot ec tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 fig u r e 29 . i 2 c bu s ac w a ve fo rm s an d m e a su r e m en t circ uit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 figu re 3 0 . spi tim i ng d i ag ra m - sla ve m o d e a n d cp ha = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 fig u r e 31 . spi t i min g dia g r a m - slave mo de an d cpha = 1 (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 f i gu re 3 2 . spi tim i ng d i ag ra m - m a s t e r m o de (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 9 fig u r e 33 . i 2 s slav e timing diagram (philips protoc ol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 fig u r e 34 . i 2 s master timing diag ram (philips protocol) (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1 figu re 3 5 . u sb otg fs tim i n g s : d e f i nit i on o f d a t a sig n a l r i se a n d f a ll t i me . . . . . . . . . . . . . . . . . . . . 9 3 figu re 3 6 . u l p i t i min g d i ag ra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 figu re 3 7 . e th er n e t sm i t i min g dia g r a m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 figu re 3 8 . e th er n e t rm ii tim i ng d i a g r a m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 6 figu re 3 9 . e th er n e t m ii t i min g d i ag ra m . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 figu re 4 0 . a dc ac cu ra cy cha r act e r i stic s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 0 figu re 4 1 . t ypic al co nn ec tio n dia g r a m usin g th e adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 0 0 fig u r e 42 . p o w e r supp ly an d re f e re nce de co up ling ( v re f + n o t co nn e cte d to v dda ) . . . . . . . . . . . . . 1 0 1 fig u r e 43 . p o w e r supp ly an d re f e re nce de co up ling ( v re f + con nect ed t o v dd a ) . . . . . . . . . . . . . . . . 1 0 1 figu re 4 4 . 1 2 - b i t bu ff er ed / n o n - b u ff e r e d d a c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figu re 4 5 . a syn ch ro n o u s no n- m u lt iple xe d sram /psr am /no r r e a d wa ve fo rm s . . . . . . . . . . . . . . 1 0 5 figu re 4 6 . a syn ch ro n o u s no n- m u lt iple xe d sram /psr am /no r w r ite w a ve fo rm s . . . . . . . . . . . . . . 1 0 6 list of figures stm32f205xx, stm32f207xx 8/147 doc id 15818 rev 5 figu re 4 7 . a syn ch ro n o u s mu ltip lex e d psr am /no r r e a d wa ve fo rm s . . . . . . . . . . . . . . . . . . . . . . . . 1 0 7 figu re 4 8 . a syn ch ro n o u s mu ltip lex e d psr am /no r w r ite w a v e fo r m s . . . . . . . . . . . . . . . . . . . . . . . 1 0 9 figu re 4 9 . s yn ch ro no u s m u ltip le xe d no r/p s ram r e a d tim i ng s . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 0 figu re 5 0 . s yn ch ro no u s m u ltip le xe d psra m writ e tim i ng s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 2 figu re 5 1 . s yn ch ro no u s n o n - mu ltip lex e d n o r/ psram r e ad tim i n g s . . . . . . . . . . . . . . . . . . . . . . . . 1 1 4 figu re 5 2 . s yn ch ro no u s n o n - mu ltip lex e d ps ram wr ite tim i n g s . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 5 figu re 5 3 . p c c a r d / c o m p a c tfla sh co nt ro ller wa ve fo rm s fo r c o m m on m e m o r y r e a d ac ce ss . . . . . . 1 1 6 figu re 5 4 . p c c a r d / c o m p a c tfla sh co nt ro ller wa ve fo rm s fo r c o m m on m e m o r y w r ite a cce ss . . . . . . 1 1 7 fig u r e 55 . p c ca rd /com pact f lash con t r o lle r wavef o r m s f o r at tr ibu t e m e mo ry rea d ac ce ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 8 fig u r e 56 . p c ca rd /com pact f lash con t r o lle r wa ve fo rm s fo r a t t r ib ut e me m o r y w r ite ac ce ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1 9 figu re 5 7 . p c c a r d / c o m p a c tfla sh co nt ro ller wa ve fo rm s fo r i / o sp ac e re ad a c c e ss . . . . . . . . . . . . 1 1 9 figu re 5 8 . p c c a r d / c o m p a c tfla sh co nt ro ller wa ve fo rm s fo r i / o sp ac e writ e ac ces s . . . . . . . . . . . . 1 2 0 figu re 5 9 . n and co n t ro lle r w a ve fo rm s fo r re ad a cce ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2 figu re 6 0 . n and co n t ro lle r w a ve fo rm s fo r writ e acc e s s . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 2 figu re 6 1 . n and co n t ro lle r w a ve fo rm s fo r com m o n me m o r y r e a d a cce ss . . . . . . . . . . . . . . . . . . . . 1 2 2 figu re 6 2 . n and co n t ro lle r w a ve fo rm s fo r com m o n me m o r y w r ite a c c e ss . . . . . . . . . . . . . . . . . . . . 1 2 3 figu re 6 3 . s dio h i g h - s p e e d m o d e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4 figu re 6 4 . s d d e f a u lt m o d e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 4 fig u r e 65 . l qfp6 4 ? 10 x 1 0 mm 64 pin low- pr of ile qu ad f l at p a ckage o u t line . . . . . . . . . . . . . . . . 127 fig u r e 66 . r ecom men ded fo ot pr int (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 7 figu re 6 7 . w l c sp6 4+ 2 - 0 . 4 0 0 m m p i tch w a f e r le ve l ch ip size p a c k a g e o u t line . . . . . . . . . . . . . . . 1 2 8 fig u r e 68 . l qfp1 00, 14 x 1 4 mm 10 0- pin lo w- pr of ile qu ad f l at packag e out lin e . . . . . . . . . . . . . . . 129 fig u r e 69 . r ecom men ded fo ot pr int (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 9 fig u r e 70 . l qfp1 44, 20 x 2 0 mm, 14 4-p i n low- pr of ile qua d fla t p a cka ge o u t line . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 fig u r e 71 . r ecom men ded fo ot pr int (1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 0 fig u r e 72 . l qfp1 76 - l o w p r o f ile q u a d fla t p a cka ge 2 4 24 1. 4 mm, pa ckag e ou tlin e . . . . . . . . 131 f i gu re 7 3 . u f b g a 17 6+ 25 - u l tra t h in f i ne p i tch b a ll gr id ar ra y 10 10 0. 6 mm , pa ck ag e ou tlin e . 1 3 2 figu re 7 4 . r e g u l at or b y p a s s /r eg u l ato r o ff . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 6 figu re 7 5 . r e g u l at or b y p a s s /r eg u l ato r o ff a n d int e r n a l r e s e t of f . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 6 figu re 7 6 . u sb otg fs p e r i ph e r a l -o nly co n n e ctio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 7 figu re 7 7 . u sb otg fs h o s t -o n l y co n n e ct i on . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 7 figu re 7 8 . o tg fs c o n n e c t i on d u a l -r o l e w i th in ter n al p h y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 8 figu re 7 9 . u sb otg hs pe rip h e r al- o n l y c o n n e c t ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 8 figu re 8 0 . u sb otg hs ho st- o n l y co nn ec tio n . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 9 figu re 8 1 . o tg hs co nn e ctio n du a l - r o l e wit h e xt e r n a l ph y . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 9 figu re 8 2 . c o m p l e t e au d i o pla ye r solu tio n 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figu re 8 3 . c o m p l e t e au d i o pla ye r solu tio n 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figu re 8 4 . a ud io p l ay er so lut i on u sin g pll , pll i 2 s , usb an d 1 cry sta l . . . . . . . . . . . . . . . . . . . . . . 1 4 1 figu re 8 5 . a ud io pl l (pl l i 2s ) p r o vid in g a cc u r a t e i2 s clo ck . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 4 1 figu re 8 6 . m ast e r clo c k (m ck ) u s e d to d r ive t h e e x te rn a l a u d i o dac . . . . . . . . . . . . . . . . . . . . . . . . 1 4 2 figu re 8 7 . m ast e r clo c k (m ck ) n o t u s e d to d r ive th e e x te rn a l au d i o dac . . . . . . . . . . . . . . . . . . . . . 1 4 2 stm32f205xx, stm32f207xx introduction doc id 15818 rev 5 9/147 1 intr oduction th is d a t a she e t p r o vide s t he d e scr i p t io n of th e stm3 2f2 05xx a n d stm 32f 207 xx line s of micr ocon tr olle rs . f o r mor e d e t a ils on t h e wh ole stm i cr oe lectr o n i cs stm3 2? f a m ily , plea se re f e r to section 2 .1: full compatib ility throughout the f a mily . th e stm3 2f2 05xx a n d stm 32f 207 xx da ta sh ee t shou ld be r e a d in conju n ctio n with t h e stm 32f 20x/ s tm32 f21 x r e f e r ence ma n u a l . f o r inf o r m a t io n on pr og r a mmi ng, er a s in g an d pr ot ectio n of th e int e r nal fla s h m e mo r y , p l ease r e f e r t o t h e stm 32f 20x/ s tm32 f21 x f l a sh pr og r a mming m a n u al. th e re f e re nce an d flash p r og r a mm ing ma n uals ar e bo th a v aila b l e fr om t h e st mic r o e le ct ro nic s web sit e www .st.com . f o r inf o r m a t io n on t h e cor t e x?- m3 cor e ple a se re f e r t o t he cor t e x?- m3 t e ch nical ref e r e n c e m a n u al, a v aila b l e f r om t he www .a r m .c om we bsit e at th e f o llo win g ad dr e ss: h t t p : / / in f o cent er . a r m . c o m / help / inde x. jsp? to pic=/ com .a r m . d o c . d d i 03 37e /. description stm32f205xx, stm32f207xx 10/147 doc id 15818 rev 5 2 description th e stm3 2f2 05xx a n d stm 32f 207 xx f a mily is ba sed on t h e high -p er f o r m a n ce arm ? cor t e x ?- m3 3 2 - b it ri sc cor e ope r a t i n g at a f r equ en cy of u p t o 120 m h z. the f a mi ly in co r p or a t e s hig h - s p e e d emb edd ed me mor i es ( f lash me mor y u p t o 1 mb yt e , u p to 12 8 k b y te s o f s yst em sr am ), up to 4 k b y te s of ba c k u p sram , an d an e x t e n s iv e r a ng e of enhanced i/os and per i pher als connected to tw o apb b u ses , tw o a hb b u ses and a 32-bit m u lti-ah b b u s matr ix . th e de vices also f e a t u r e a n ada pt iv e re al- t im e mem o r y acceler a t o r ( a r t acceler a t o r?) which a llo ws to a c h i e v e a p e r f o r ma nce equ iv ale n t t o 0 w a it st at e pr og r a m e x ecut ion f r o m fla s h memo r y at a cpu fr eq uen cy up t o 12 0 m hz. th is pe rf or man c e has bee n v a lid at ed u s in g th e cor e ma r k be nchma r k. all de vices of f e r t h r e e 1 2 - b it adcs , t w o d a cs , a lo w-p o w e r r t c , tw elv e ge ner al- pur po se 1 6 - b it t i me rs in cludin g tw o pwm t i me rs f o r mot o r co nt ro l, t w o ge ner al- pur po se 3 2 - b it t i me rs . a t r ue n u mb er r a ndo m ge ner a t or ( r ng ). the y a l so f e a t u r e st an dar d an d ad v a nced com m u nicat i on i n t e rf a c e s . ne w ad v ance d per ip he r a ls include an sdio , an e nha nced f l e xib le st at ic me mor y co nt ro l (fsm c) int e r f a ce (f or de vices o f f e r e d in pa c k a g e s o f 1 00 p i ns a nd mo re ), and a cam e r a in te rf ace f o r cmo s se nsor s . up to t h ree i 2 cs three spis , tw o i 2 ss . t o ach i e v e au dio class a c cur a cy , th e i 2 s pe r i phe r a ls ca n be cloc k e d via a d e d i ca te d int e r nal au dio pl l or via an e x te r n a l pl l t o allo w sy nc hr on iza t io n. 4 usar ts an d 2 u a r t s an usb o t g full-speed and a usb o t g full-s peed with high-s peed capability (w ith the ulpi), tw o c a n s an sd io interf ace eth e r net and th e ca mer a int e r f a c e a v ai lab l e on stm 32f2 0 7 x x de vices only . th e stm3 2f2 05xx a n d stm 32f 207 xx f a mily ope r a t e s in t he ?4 0 t o +1 05 c t e mp er a t u r e r a ng e fr om a 1 . 8 v t o 3. 6 v p o w e r su pp ly . a comp re hen siv e set of po w e r- sa ving mo de a llo ws th e de sig n of lo w- po w e r ap plicat ion s . th e stm3 2f2 05xx a n d stm 32f 207 xx f a mily of f e rs de vices in f o ur p a c kag es r ang ing f r om 6 4 pins t o 176 p i ns . the se t of includ ed pe r i ph er a l s chan ge s with th e de vice chosen . th ese f eat u r es mak e th e stm32 f 20 5xx a nd stm3 2f2 0 7 x x micro c o n t r o ller f a m ily suit ab le f o r a w i de r a ng e of a p p lica t io ns : mo to r dr iv e a nd ap plicat ion co nt ro l me dical equ ipme nt in d u s t r i al ap p licat ion s: pl c , in v e r t e r s , c i rc uit br ea k e rs pr int e r s , a n d scann er s alar m syst ems , video intercom, and h v a c home a udio app liance s fig u r e 4 sho w s t he g ene r a l b l oc k d i ag r a m of th e de vice f a mily . stm32f205xx, stm32f207xx description doc id 15818 rev 5 11/147 t a b l e 2. st m32 f 20 5xx a nd stm3 2f2 07x x f e a t u r es a nd peri ph era l co unt s p erip h erals s tm32f 205rx s t m 32f 205vx s t m32f 205zx stm32f 207vx s t m 32f20 7zx s t m 32f20 7ix f l ash memor y in kb y tes 128 256 512 768 1024 128 256 512 768 102 4 256 51 2 768 1024 25 6 5 12 76 8 10 24 256 512 768 1024 256 512 768 1024 sram in kb y t es sys t em 64 (48+16) 96 (80+16) 128(112+16) 64 (48+16) 96 (80+16) 128 (1 12+16) 96 (80+16) 128 (112 + 1 6 ) 128 (1 12+16) bac k up 4 4 4 4 fsmc memor y controller no ye s ether net no ye s time rs gener al- pur pose 10 adv a nced -c ont rol 2 basi c 2 ra ndom n umber gen er ator ye s co mm. interf aces spi / (i 2 s) 3 (2 ) i 2 c 3 usar t ua r t 4 2 usb o t g fs 1hs/fs 1fs , 1hs/fs usb o t g hs can 2 ca mer a in terf ace n o ye s gpios 5 1 8 2 114 82 114 1 40 12-bit adc nu mber of channe ls 3 16 16 24 16 24 24 12-bit d a c nu mber of channe ls ye s 2 description stm32f205xx, stm32f207xx 12/147 doc id 15818 rev 5 maxim u m c p u frequency 120 mhz oper ating v o ltage 1.8 v to 3.6 v oper ating temp er atures ambie nt temper atures: ?40 to +85 c /?40 to +105 c j un c tion temper a t ure: ?40 to + 125 c p ac k age lqf p 64 wl csp64+2 lqf p 100 lqfp144 lqfp100 lqf p 144 lqf p 1 7 6 (1) uf b g a176 1. package n o t in p r oductio n and available for development only. t a b l e 2. st m32 f 20 5xx a nd stm3 2f2 07x x f e a t u r es a nd peri ph era l co unt s (co n ti n u e d ) p erip h erals s tm32f 205rx s t m 32f 205vx s t m32f 205zx stm32f 207vx s t m 32f20 7zx s t m 32f20 7ix stm32f205xx, stm32f207xx description doc id 15818 rev 5 13/147 2. 1 full compati b ili ty t h r o ughout the fami l y th e stm3 2f2 05xx a n d stm 32f 207 xx const i tu t e th e stm32 f 20 x f a m ily whose me mbe r s ar e fu lly p i n- to -p in , so ft w a r e an d f e at ur e com p at ib le , allo w i ng t h e u se r t o tr y d i ff e r e n t me mor y d e n s it ies an d per ip he r a ls f o r a g r e a t e r deg r e e o f f r e edo m dur ing t he d e v e lo pme n t cyc le . the stm32f205xx and stm32f 207x x de v i ces maintain a close compatibility with the wh ole st m 3 2 f 10 xx x f a m ily . all fu nct i on a l pin s ar e pin - t o - p in c o m p at ib le . th e stm 32f 205 xx an d stm32 f 20 7xx, ho w e v e r , a r e n o t dro p - i n re pla c e m en ts f o r t he stm32f10xxx de vic e s : the tw o f a milies do not ha v e the same po w e r s cheme , and so their p o w e r p i ns a r e d i ff er en t. no net he less , t r a n sitio n fr om t h e stm3 2f1 0 xxx to t h e stm 32f 20x f a m ily r e ma ins simp le as only a f e w pins ar e impa ct e d . fig u r e 1 comp at ib le boa rd d e sign b e t w ee n t he stm3 2f2 0 x a n d t h e st m32 f 10 xxx f a m ily . figu re 1. compa t ib le boar d des i gn: lqfp14 4 3 1 71 1 3 6 3 7 72 7 3 10 8 144 109 v ss 0 re s i s tor or s older ing b r idge pre s ent f or the s tm 3 2f10xxx config u r a tion, not pre s ent in the s tm 3 2f20xxx config u r a tion 106 v ss 3 0 t w o 0 re s i s tor s connected to: - v ss f or the s tm 3 2f10xxx - v dd (with a 10 nf deco u pling c a p a citor f or the s tm 3 2f20xxx v ss v dd v ss v ss a i15960 14 3 v ss v dd description stm32f205xx, stm32f207xx 14/147 doc id 15818 rev 5 figu re 2. compa t ib le boar d des i gn: lqfp10 0 figure 3. compatible board design: lqfp64 20 49 12 5 26 50 51 75 100 76 7 3 19 v ss v ss v dd v ss v ss v ss 0 re s i s tor or s older ing b ri d g e pre s ent f or the s tm 3 2f10xxx config u r a tion, not pre s ent in the s tm 3 2f20xxx config u r a tion a i15961 t w o 0 re s i s tor s connected to: - v ss f or the s tm 3 2f10xxx - v dd f or the s tm 3 2f20xxx 99 v ss v dd 3 1 116 17 3 2 33 4 8 64 49 47 v ss v ss v ss v ss 0 re s i s tor or s older ing b r idge pre s ent f or the s tm 3 2f10xxx config u r a tion, not pre s ent in the s tm 3 2f20xxx config u r a tion a i15962 stm32f205xx, stm32f207xx description d o c id 158 18 re v 5 1 5/1 4 7 2. 2 de vice o v er vie w fi gu re 4. stm 32f 20x b l oc k di a g ra m ' 0 ) / 0 / 2 4 ! ! ( " ! 0 " % 8 4 ) 4 7 + 5 0 ! & 0 ! ; = ' 0 ) / 0 / 2 4 " 0 " ; = 4 ) - 0 7 - c o m p l c h a n n e l s 4 ) - ? # ( ; = . c h a n n e l s 4 ) - ? # ( ; = % 4 2 " + ) . a s ! & 4 ) - 0 7 - ' 0 ) / 0 / 2 4 # 0 # ; = 5 3 ! 2 4 2 8 4 8 # + # 4 3 2 4 3 a s ! & ' 0 ) / 0 / 2 4 $ 0 $ ; = ' 0 ) / 0 / 2 4 % 0 % ; = ' 0 ) / 0 / 2 4 & 0 & ; = ' 0 ) / 0 / 2 4 ' 0 ' ; = 3 0 ) - / 3 ) - ) 3 / 3 # + . 3 3 a s ! & ! 0 " - ( z ! 0 " - ( z a n a l o g i n p u t s c o m m o n t o t h e ! $ # s a n a l o g i n p u t s c o m m o n t o t h e ! $ # 6 $ $ 2 % & ? ! $ # a n a l o g i n p u t s t o ! $ # c h a n n e l s % 4 2 a s ! & c h a n n e l s % 4 2 a s ! & c h a n n e l s % 4 2 a s ! & c h a n n e l s % 4 2 a s ! & 2 8 4 8 # + 5 3 ! 2 4 2 8 4 8 # + 5 3 ! 2 4 2 8 4 8 a s ! & 5 ! 2 4 2 8 4 8 a s ! & 5 ! 2 4 - / 3 ) $ / 5 4 - ) 3 / $ ) . 3 # + # + 3 0 ) ) 3 . 3 3 7 3 - # + a s ! & - / 3 ) $ / 5 4 - ) 3 / $ ) . 3 # + # + 3 0 ) ) 3 . 3 3 7 3 - # + a s ! & 3 # , 3 $ ! 3 - " ! a s ! & ) # 3 - " 5 3 3 # , 3 $ ! 3 - " ! a s ! & ) # 3 - " 5 3 4 8 2 8 b x # ! . 4 8 2 8 b x # ! . $ ! # ? / 5 4 a s ! & $ ! # ? / 5 4 a s ! & ) 4 & 7 7 $ ' + " " + 3 0 2 ! - 2 4 # ? ! & / 3 # ? ) . / 3 # ? ) . / 3 # ? / 5 4 / 3 # ? / 5 4 . 2 3 4 6 $ $ ! 6 3 3 ! 6 # ! 0 6 # ! 0 5 3 ! 2 4 2 8 4 8 # + # 4 3 2 4 3 a s ! & s m c a r d i r $ ! s m c a r d i r $ ! s m c a r d i r $ ! s m c a r d i r $ ! b b b b b b b b # 4 3 2 4 3 a s ! & # 4 3 2 4 3 a s ! & 3 $ ) / - - # $ ; = # - $ # + a s ! & 6 " ! 4 t o 6 $ - ! ! ( " ! 0 " $ - ! 3 # , 3 $ ! 3 - " ! a s ! & ) # 3 - " 5 3 ' 0 ) / 0 / 2 4 ( 0 ( ; = ' 0 ) / 0 / 2 4 ) 0 ) ; = * 4 ! ' 3 7 $ " 5 3 3 " 5 3 ) " 5 3 . 6 ) # % 4 - - 0 5 . * 4 2 3 4 * 4 $ ) * 4 $ / 3 7 $ * 4 $ / 4 2 ! # % 3 7 / 4 2 ! # % # , + 4 2 ! # % $ ; = * 4 # + 3 7 # , + % t h e r n e t - ! # $ - ! - ) ) o r 2 - ) ) a s ! & - $ ) / a s ! & & ) & / 5 3 " $ - ! & ) & / / 4 ' ( 3 $ 0 $ - 5 , 0 ) # + $ $ ) 2 3 4 0 . 8 4 $ - ! 3 t r e a m s & ) & / $ - ! 3 t r e a m s & ) & / ! # # % , # ! # ( % 3 2 ! - + " 3 2 ! - + " # , + . % ; = ! ; = $ ; = / % . 7 % . . " , ; = . , . 2 % ' . 7 ! ) 4 ) / 2 $ 9 # $ . ) / 2 $ ) / 7 2 ) . 4 ; = ) . 4 . . ) ) 3 a s ! & 3 # , 3 $ ! ) . 4 . ) $ 6 " 5 3 3 / & # a m e r a i n t e r f a c e ( 3 9 . # 6 3 9 . # 0 ) 8 # , + $ ; = 5 3 " 0 ( 9 / 4 ' & 3 $ 0 $ - & ) & / & ) & / ! ( " - ( z 0 ( 9 & ) & / 5 3 ! 2 4 - " p s 4 e m p e r a t u r e s e n s o r ! $ # ! $ # ! $ # ) & ) & 6 $ $ ! 6 $ $ ! 0 / 2 0 $ 2 3 u p p l y 6 $ $ ! s u p e r v i s i o n 0 6 $ 2 e s e t ) n t 0 / 2 8 4 ! , / 3 # - ( z 8 4 ! , k ( z ( # , + x - ! . ! ' 4 2 4 # 2 # ( 3 & # , + 2 # , 3 3 t a n d b y ) 7 $ ' 6 " ! 4 6 $ $ ! 6 $ $ ! 7 5 2 e s e t c l o c k c o n t r o l 0 , , 0 # , + x i n t e r f a c e 6 $ $ t o 6 6 3 3 6 o l t a g e r e g u l a t o r 6 t o 6 6 $ $ 0 o w e r m a n a g m t 6 $ $ 2 4 # ? ! & " a c k u p r e g i s t e r 3 # , 3 $ ! ) . 4 . ) $ 6 " 5 3 3 / & ! ( " b u s m a t r i x 3 - ! 0 " - ( z ! ( " - ( z , 3 , 3 c h a n n e l s a s ! & c h a n n e l a s ! & c h a n n e l a s ! & 4 ) - b b b 4 ) - c h a n n e l s a s ! & 4 ) - c h a n n e l a s ! & b b 4 ) - c h a n n e l a s ! & b " / 2 $ ! # $ ! # & l a s h - b y t e 3 2 ! - 0 3 2 ! - . / 2 & l a s h 0 # # a r d ! 4 ! . ! . $ & l a s h % x t e r n a l m e m o r y c o n t r o l l e r & 3 - # 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - 4 ) - a i b c o m p l c h a n n e l s 4 ) - ? # ( ; = . c h a n n e l s 4 ) - ? # ( ; = % 4 2 " + ) . a s ! & & ) & / 2 . ' ! 2 - # o r t e x - - ( z ! 2 4 a c c e l e r a t o r description stm32f205xx, stm32f207xx 16/147 doc id 15818 rev 5 2.2.1 arm ? cor t e x ?-m3 core with embedded flash and sram th e arm co r t e x - m 3 pr ocessor is t he lat e st gen er a t io n of arm pr ocessor s f o r emb edd ed syst e m s . i t w a s d e v e lo pe d to p r o v ide a lo w- co st plat f o r m th at m eet s t h e nee ds of m c u imp l em ent at ion , wit h a re duce d pin cou n t a nd lo w-p o w e r co nsump t io n, wh ile de liv e r ing o u t s t a n d in g co mpu t a t iona l p e r f o r ma nce an d an a d v a n c e d re sp on se t o int e rr up t s . th e arm co r t e x - m 3 32 -b it ri sc pr ocessor f e a t u r e s e xcep t io nal cod e - e f f icien c y , d e liv er in g t h e h i gh -pe r f o r m an ce e x pect e d f r o m an arm co re in th e mem o r y siz e usua lly a s sociat e d wit h 8- a nd 1 6 -b it d e vice s . wit h its emb e d ded arm cor e , t he stm3 2f2 05xx and st m32 f 20 7xx f a mily is comp at ib le wit h all arm t o o l s a nd sof t w ar e . fig u r e 1 sho w s t he g ene r a l b l oc k d i ag r a m of th e stm32 f 20 x f a m ily . 2.2.2 memor y pr otection unit th e m e mo r y pr ot ect i on unit ( m pu) is u s e d t o se par at e t h e pr ocessing of ta sks f r o m t h e dat a p r o t e c t i on . the mpu ca n ma na ge u p t o 8 pr ot ect i on ar eas t h a t ca n all be f u r t he r d i vided up in to 8 sub a r eas . t he pro t ectio n a r e a siz e s a r e bet w e en 32 b y t e s an d t h e wh ole 4 g i gab yte s o f ad dr essa b l e mem or y . th e me mor y pr ot ect i on u n it is espe cia lly h e lpf u l f o r app lica t io ns wh er e so me cr it ica l o r cer t if ied cod e has to be pr ot ect ed a gain s t t he misbe h a v i o r of ot he r t a sks . i t is u s ually ma na ged b y an r t os (r eal- t ime op er a t in g syst em) . i f a p r o g r a m a c cesses a memo r y loc a t i on th a t is pr o h ib ite d b y the m p u , t h e r t os ca n de te ct it a n d t a k e a c tio n . i n an r t os e n vir onm ent , t h e k e r n el can dyna mically upd at e t he mpu are a set t in g, based o n t he pr oc es s t o be e x e c u t ed . th e mpu is op tio nal a nd can b e b ypa sse d f o r ap plicat ion s t h a t do n o t nee d it. 2.2.3 adaptive real-time memor y accelerator (ar t accelerator?) the ar t acceler a tor? is a memor y acc e ler a to r which is o p t i miz e d f o r stm3 2 indu str y - st and ar d arm ? cor t e x?- m3 pr ocessor s . i t b a la nces t h e inhe re nt p e r f o r ma nce ad v ant ag e o f t he arm co r t e x - m 3 o v er flash me mor y t e chn o lo gies , which no r m a lly re qu ire s t he p r o c e s sor to w a it f o r th e flash me mor y a t h i ghe r op er a t in g fr eq ue ncies . t o rele ase t he p r oce s sor fu ll 1 50 dmi ps p e r f o r ma nce at th is f r e que ncy , th e acceler a t o r imp l em ent s a n inst r u ctio n pr ef et ch que ue a nd b r anch cache wh ich in crea ses p r o g r a m e x e c u t i on spee d f r om t h e 128 -b it fla s h m e mo r y . based o n corema r k be nchma r k, t he p e r f o r ma nce achie v e d t han ks t o th e ar t a c cele r a t o r is e quiv a lent to 0 w a it st at e pr og r a m e x e c u t i on f r o m f l ash mem o r y at a cpu f r e que ncy u p to 1 2 0 m hz. 2.2.4 embed ded flash memor y th e stm3 2f2 0 x d e vices e m be d a 12 8- bit wide flash me mor y of 12 8 kb yt es , 256 kb yte s , 512 kb yt e s , 76 8 kb yt e s or 1 m b yt es a v aila b l e f o r sto r ing p r og r a ms an d dat a. stm32f205xx, stm32f207xx description doc id 15818 rev 5 17/147 2.2.5 crc (c yc lic redundanc y c hec k) calculation unit th e crc ( c yclic r e d und ancy ch ec k) calcula t ion u n it is used to get a crc code fr om a 3 2 - b it d a t a w o rd a nd a f i x e d ge ner at or p o lyno mial. am on g ot he r ap p licat ion s , c rc- ba se d te ch niq u e s ar e us ed to v e r i fy d a t a t r an sm issio n o r st or a ge int e g r ity . i n th e sco p e o f t he en/i ec 6 0 3 35- 1 sta nda rd , t h e y o f f e r a mea n s of v e r i fying t h e flash me mor y in te g r ity . th e crc ca lcu l at ion u n it help s comp ut e a sof t w ar e sign at ur e du r i ng r u n t ime , t o be com par ed wit h a re f e re nce signa tu re g e n e r a te d at li nk-t ime a nd sto r e d at a giv e n m e mo r y locat i on . 2.2.6 t r ue random n u m ber g enerator (rng) all stm32f2xxx products embed a t r ue rn g that deliv ers 32-bit r andom n u mbers p r o duced b y an int e g r at ed a nalo g circuit . 2.2.7 embed ded sram all stm3 2f2 0 x pro d u c t s e m be d up t o 1 28 kb ytes of syst em sram acce sse d (r ea d/ wr it e ) at cpu cloc k spee d wit h 0 w a it st at es , plu s 4 kb yt es of bac kup sram. 2.2.8 multi-ahb b u s matrix the 3 2 - b it m u lti-a h b b u s m a tr ix in te rco n n e cts a ll th e m a st er s ( c pu , dm as , eth e r n e t, usb hs) a nd t h e sla v es ( f lash me mor y , ram, f s mc , ahb and apb p e r i ph er a l s) an d en su re s a sea m less a n d e f f i cien t op er a t io n e v en wh en se v e r a l high -spe ed p e r i ph er a l s w o r k sim u lt an eou sly . figu re 5. mu lt i-ahb mat r ix ! 2 - # o r t e x - ' 0 $ - ! ' 0 $ - ! - ! # % t h e r n e t 5 3 " / 4 ' ( 3 " u s m a t r i x 3 3 3 3 3 3 3 3 3 ) # / $ % $ # / $ % ! 2 4 ! # # % , & l a s h m e m o r y 3 2 ! - + b y t e 3 2 ! - + b y t e ! ( " p e r i p h ! ( " p e r i p h & 3 - # 3 t a t i c - e m # t l - - - - - - - ) b u s $ b u s 3 b u s $ - ! ? 0 $ - ! ? - % - $ - ! ? - % - $ - ! ? 0 % 4 ( % 2 . % 4 ? - 5 3 " ? ( 3 ? - a i b ! 0 " ! 0 " description stm32f205xx, stm32f207xx 18/147 doc id 15818 rev 5 2.2.9 dma th e f l e x ib le 16- str e a m g e n e r a l-pu r p ose dmas ( 8 st r eam s f o r dma1 a nd 8 st re ams f o r dma2) ar e ab le t o man age m e mo r y -t o - me mor y , per ip he r a l- to -me m or y a n d me mor y -t o- per i pher al tr ansf ers . the y s hare some centr a liz ed fifos f o r apb/ah b per i pher als , suppor t b u rst tr ansf er and are design ed to pro v ide the maxim u m per ipher al bandwidth (ah b/apb) a nd pe rf or man c e . th e t w o dma co nt ro ller s supp or t cir c u l ar b u ff er man age men t , so th at n o specif ic cod e is n eed ed whe n th e cont r o ller re aches th e en d of th e b u ff e r . the t w o dm a con t r o lle rs also h a v e a d oub le b u f f er in g f e at ur e , which au to mat e s th e use an d s w it chin g of t w o memo r y b u f f er s with o u t r equ ir ing a n y special cod e . ea ch st re am is con n e c t e d t o d edicat e d har dw a r e dma r equ ests , with su ppo r t f o r sof t w ar e t r igg e r o n ea ch st re am. co nf igu r at ion is mad e b y sof t w a r e and t r a n sf e r siz e s be tw een sou r ce an d de st ina t io n ar e ind epe nd ent . th e dma ca n be use d wit h t h e ma in pe r i ph er al s: spi an d i 2 s i 2 c usar t an d u a r t g e n e r a l -p u r p o s e , b a sic an d ad v a nc ed -c on tr ol tim e r s t i m x da c sdio camer a interf ace (dcmi) adc . 2.2.10 fsmc (fle xib l e static memor y contr o ller) th e fsmc is em bed de d in th e stm3 2f2 05xx a n d stm 32f 207 xx f a mily . i t ha s f o u r chip se lect ou tp ut s sup p o r t i ng th e f o llo win g mod e s: pccar d / c o m pa ct flash , sram , psram , nor flash a nd nand flash. fu nct i ona lit y o v er vie w : wr it e fi fo code e x ecut ion f r o m e xte r n al mem o r y e xcept f o r nand flash a nd pc car d the ta rg et ed f r e que ncy , f clk , is e q u a l to hc lk/ 2 , so e xte r n a l a cce ss is a t 60 m h z when hclk is a t 120 mhz a nd e xt e r nal access is at 30 mhz whe n hcl k is at 60 mhz lcd parallel interface th e fsmc ca n be con f ig ur ed t o int e r f ace seam lessly wit h mo st g r a phic lcd con t r o lle rs . i t sup por t s t h e in te l 8 0 8 0 and m o t o r o la 6 800 m ode s , a nd is fle x ib le e nou gh t o ad apt t o spec ific lcd interf aces . this lcd par a llel interf ace c a pability mak e s it eas y to b u ild c o st- e f f e ct iv e g r ap hic app lica t i ons using l c d mod u le s with e m be dd ed con t r o lle rs o r hig h p e r f o r ma nce so lut i on s usin g e xte r n al co nt ro ller s with ded ica t ed accele r a t i on . stm32f205xx, stm32f207xx description doc id 15818 rev 5 19/147 2.2.11 nested vectored inte rrupt contr o ller (nvic) th e stm 32f 205 xx a nd stm 32f 207 xx e m be d a n e ste d v e ct or ed int e r r upt con t r o lle r ab le to h and le up t o 87 maskab l e int e r r up t chan ne ls (n ot includi ng t he 16 int e r r upt line s of th e cor t e x?- m3 ) an d 16 pr io r i t y le v e ls . closely co uple d nvi c giv e s lo w- lat e n c y int e r r up t pr ocessing i n t e r r upt ent r y v e ct or t a b l e a ddr ess p a ssed dir e ct ly t o t he cor e closely c o upled nv ic c o re interf ace allo ws ea r l y pr ocessing o f int e rr up t s pr oc es sing o f late a r r i v i ng , hig h e r -p r i or ity in te rr u p t s sup por t ta il cha i nin g pr oc es sor st at e au to m a t i cally sa v e d i n t e r r upt ent r y r e sto r e d on in te rr u p t e x i t with n o inst r u ctio n o v er hea d t h is ha rd w a r e b l oc k pr o vid es fle xib le int e r r up t m a na g e m e nt f e at ur es with m i nim u m int e r r up t latency . 2.2.12 external interr upt/e vent contr oller (exti) th e e xt e r n al int e r r up t/ e v e n t co nt ro ller con s ist s o f 23 e d g e -d et ect o r lin es u sed t o ge ner a t e in te rr u p t / e v ent re que sts . each line can be ind e p end ent ly co nf igur ed t o sele ct th e t r igge r e v e n t (r isin g ed ge , f a lling e d g e , b o t h ) a n d ca n be mask ed ind epe nde nt ly . a pe ndin g r egist er m a in ta ins th e sta t u s o f th e inte r r up t r e qu es ts . th e exti c a n d e t e c t a n e x te r n a l line w i th a pulse width shor ter than the inter n al apb2 cloc k per i od. up to 140 gp ios can be connected to th e 16 e xt e r n al in te rr u p t lin es . 2.2.13 cloc ks and star tup system c loc k selec t ion is perf or med on s t ar tup , ho w e v e r , th e 16 mhz inter n al rc oscillator is se lect ed as th e de f a ult cpu clo c k on rese t. an e xte r n a l 4- 26 m h z cloc k can be se lecte d , in which case it is monitored f o r f a ilure . if f a ilu re is de te ct ed , the s yst em a u t o m a tica lly s witches bac k to the inter n al r c oscillator . a soft w a re interr upt is gener a ted if enab led. simila r l y , fu ll in te rr u p t man age men t of t he pll cloc k en tr y is a v a ilab l e when n e cessar y ( f o r e x ample if an indirectly us ed e x ter n al os cillator f a ils). the 16 mh z inter nal rc os cillator is f a ctor y-tr immed to off e r 1% acc u r a cy o v er the full t em per at ure r an ge . th e ad v anced clo c k cont r o ller clo c ks t he cor e an d all pe r i phe r a ls using a sing le cr ysta l o r os cillator . in par ticular , the ether n et and usb o t g fs per i pher als can be cloc k e d b y the sys tem cloc k . se v e r a l pr escaler s a nd pll s allo w th e co nf igur at ion of th e tw o ahb b u ses , t h e h i gh- spee d apb (apb2) and the lo w-speed apb (apb1) domai ns . the maxim u m frequency of the tw o ahb b u ses is 120 m h z and the maxim u m frequency the high-speed apb domains is 60 mhz. the maxim u m allo w ed frequency of the lo w-speed apb domain is 30 mhz. in or de r to ac hie v e a u d io cla ss pe rf or m a n ce , a s p e cif ic cr yst al c a n be u se d . in th is ca se , th e i 2 s m a ste r cloc k ca n gen er a t e all st an da rd sam p ling f r equ en cie s f r o m 8 k hz t o 9 6 khz. description stm32f205xx, stm32f207xx 20/147 doc id 15818 rev 5 2.2.14 boot modes at st ar t u p , bo ot p i ns are u s ed t o select o n e o u t o f t h r ee b oot opt io ns: bo ot fr om use r f l as h bo ot f r om syst em me mor y boo t f r o m e m be dd ed sram th e bo ot lo ad er is locat e d in syst e m m e mo r y . i t is u s ed t o re pr og r a m th e flash me mor y b y using us ar t1 (p a9/p a 1 0), usar t3 (pc10/pc 11 or pb10/pb11), c a n2 (p b5/pb6), usb o t g fs in de vice mo de ( p a9 / p a1 1/ p a 12) th rou g h dfu (de v ice f i r m w a r e up g r ad e) . 2.2.15 p o wer suppl y sc hemes v dd = 1.8 t o 3. 6 v : e x t e r n al po we r s u p p ly f o r i/o s an d th e int e r n a l r e g u l at or (w he n en ab led ) , pr o v ided e x t e r nally t h r o u gh v dd pins . on wl csp pac kag e , v dd r a ng es f r o m 1. 65 t o 3 . 6 v . v ssa , v dd a = 1 . 8 to 3. 6 v : e x t e r n a l ana log p o w e r supp lies f o r adc , d a c , reset b l oc ks , rcs an d pl l. v dd a a nd v ssa m u st b e co nn ecte d t o v dd an d v ss , respect i v e ly . v ba t = 1.65 to 3.6 v : po w e r supply f o r r t c , e x ter n al cloc k 32 k h z os cillator and bac k up re gist er s (t h r ou gh p o w e r s wit ch ) when v dd is n o t pr es en t. 2.2.16 p o wer suppl y super v isor th e de vice h a s a n int e g r a t ed po w e r - on rese t (po r ) / po w e r - d o wn r e set (pdr) cir c uit r y co up le d w i th a bro w no u t r e s e t (b or) cir c u i tr y . at p o w e r - on, bor is alw a ys act i v e , an d e n sur e s pro p e r op er a t io n sta r tin g fr om 1 . 8 v . aft e r th e 1. 8 v bor th re sh old is re ache d, t h e o p t i on b y te lo ad ing pr ocess st ar t s , e i th er t o con f ir m or m odif y d e f a u l t t h r e shold s , o r t o d i sa b l e bo r p e r m ane nt ly . thr ee bor t h re shold s ar e a v ailab l e t h r o u gh op t i on b y t e s . th e de vice r e ma ins i n rese t mo de whe n v dd is belo w a spec i f ied thres h old, v por/pdr or v bo r , wit h out th e ne ed f o r a n e x t e r n al re se t circui t. on de vice s in wlcsp pac kag e , bor ca n be in ac tiv a te d b y s e t tin g irr o ff to v dd (se e sect ion 2 .2 .1 7: v o lt ag e re gula t o r ). th e de vice also f e at ur es a n e m be dd ed pr og r a mma b le v o lt ag e det e c t o r ( pvd) t h a t mo nit o r s th e v dd /v dd a po w e r sup p ly and co mpa r es it t o t he v pvd t h r e s h o l d. an in te rr u p t ca n be g ene r a t e d wh en v dd /v dd a d r ops be lo w t h e v pvd t h r e s h o l d an d/ or wh en v dd /v dd a is high er th an t h e v pvd t h resh old. the in te rr u p t se r v ice ro ut ine can t h e n ge ner at e a w a r n ing me ssa ge an d/ or put th e mcu in to a sa f e st at e . th e pvd is e nab le d b y so f t w a re . 2.2.17 v o ltag e regulator th e re gu lat o r h a s f i v e op er a t ing mo des: regu lat o r o n ? m a i n re gu la to r m o de ( m r ) ? l o w po w e r re gu lat o r ( l pr ) ? p ow e r - d ow n regu lat o r o f f ? r e gula t or b ypass/r e g u lat o r of f ? r e gula t or b ypass/r e g u lat o r of f a nd int e r n a l r e set of f stm32f205xx, stm32f207xx description doc id 15818 rev 5 21/147 regul ator o n these m o des ar e act i va te d by def au lt o n lqf p p a cka g e s . on wlcps66 a nd ufbga1 76, t h e y ar e act i vat ed by set t in g reg o ff p i n t o v ss . v dd minim u m v a lue is 1. 8 v . th er e ar e th re e re gu lat o r o n mod e s: mr is used in th e nom ina l r e g u lat i on m ode (run ) lpr is used in th e sto p mod e s7 p o w e r-do wn is us ed in standb y mode: the reg u la to r ou tp ut is in hig h imp eda nce: t h e k e r n el circuit r y is p o w e r e d d o wn , ind u cing z e ro co nsump t io n (b ut th e cont en t s of th e re gist ers an d sram ar e lost ). regul ator off regu lat o r b ypa ss / r e gula t o r of f thi s mo de is a c t i vat e d b y set t i ng rego ff pin t o v dd . it is a v a ilab l e only on t h e ufbga and wl csp pa ckag es. the reg u la to r bypa ss/ r e g u l at or o f f mod e a llo ws to su pply exte rn ally a 1. 2 v volt a ge sour ce th ro ugh v cap_1 a nd v cap_2 pins, i n add itio n t o v dd . v dd min i m u m v a lu e is 1. 8 v . t h e f o llo win g co nd itio ns m u st be r e spe c t e d in re gul at or b ypass m ode: ?v dd sh ou ld alw a ys be h i ghe r t han v cap_1 an d v ca p _ 2 t o a v oid cur r e n t in ject ion bet w e en p o w e r d o ma ins . ? if th e t i me f o r v cap_1 an d v cap_2 t o r each 1. 08 v is f a st er t han t he t i me f o r v dd to rea ch 1. 8 v , t hen p a 0 sho u ld b e co nne cte d to t h e nrst pin ( see fig u r e 6 ). otherwis e , p a 0 should be asser t ed lo w e x ter n ally until v dd r e a c h e s 1. 8 v ( see figu re 7 ). i n re gula t o r b y p a ss o n ly m ode , p a 0 ca nno t b e used a s a gpi o pi n. regu lat o r b ypa ss / r e gula t o r of f and in te r n al re se t of f th is m o d e is ac tiva te d by se ttin g irr o ff p i n to v dd . i rro ff ca nn o t b e ac tiv a te d in conjunction with r egoff. this mode is a v a ilab l e on ly o n th e wl csp pa c ka g e . it allo ws to supply e x ter n ally a 1 . 2 v v o lt ag e so ur ce t h rou g h v cap_1 an d v ca p _ 2 pin s , in ad dit i on t o v dd . v dd min i m u m v a lu e is 1. 65 v . the f o llo win g co nd itio ns m u st be r e spe c t e d in re gul at or b ypass m ode (see fig u r e 8 ): ?v dd sh ou ld alw a ys be h i ghe r t han v cap_1 an d v ca p _ 2 t o a v oid cur r e n t in ject ion bet w e en p o w e r d o ma ins . ? e xt er nal r e set sh ould b e used t o co v e r bo t h cond itio ns: u n t il v cap_1 and v cap_2 rea ch 1. 08v an d un til v dd re ac he s 1 . 6 5 v p a 0 ca n be u s e d as a st a nda rd g p io p i n. description stm32f205xx, stm32f207xx 22/147 doc id 15818 rev 5 figu re 6. st ar t up in re gulat or b y pas s /re gulat or off mode: slo w v dd slope - po we r - do wn re se t ris e n a f t e r v cap_1 /v cap_2 st abi l i zat i on figu re 7. st ar t up in re gulat or b y pas s /re gulat or off mode: slo w v dd slope - po wer - d o wn res e t rise n bef o r e v ca p _ 1 /v c a p_2 s t a b i liz at ion figure 8. sartup in regulator bypass/regulator off and internal reset off 6 $ $ t i m e 6 0 $ 2 6 6 # ! 0 ? 6 # ! 0 ? 6 t i m e 0 ! t i e d t o . 2 3 4 . 2 3 4 6 $ $ t i m e 6 0 $ 2 6 6 # ! 0 ? 6 # ! 0 ? 6 t i m e 0 ! a s s e r t e d e x t e r n a l l y . 2 3 4 6 $ $ t i m e 6 6 # ! 0 ? 6 # ! 0 ? 6 t i m e . 2 3 4 6 stm32f205xx, stm32f207xx description doc id 15818 rev 5 23/147 2.2.18 real-time c l oc k (r tc), bac kup sram and bac kup register s th e ba c k u p do main o f t h e stm 32f 205 xx an d stm32 f 20 7xx in cl u des: t h e r e al- tim e cloc k ( r t c ) 4 kb yt es of bac kup sram 20 b a c kup r e g i st er s t h e r t c pr o vid es a se t of co nt in uo us ly r u nn in g co un te rs wh ich ca n be u se d with su ita b le sof t w ar e t o pr o vid e a clo c k ca len dar f unct i on , a n a l ar m int e r r up t and a p e r i o d ic int e r r up t. i t is cloc k e d b y a 32.768 khz e x ter nal cr ystal, reso nator or oscillator , th e inter n al lo w-po w e r rc os cillator or the high-speed e x ter nal c l oc k divided b y 128. th e inter n al lo w-speed rc has a t ypical f r eq ue ncy of 32 khz. the r t c can be ca libr a te d using a n e xte r n al 512 hz out pu t t o com pen sa te f o r an y nat ur al qua r t z de via t io n. th e r t c f e a t u r e s cale nda r re gist er s with se co nds , min u te s , h our s , w e e k d a y , dat e , m ont h, y e ar . t w o ala r m r egist er s ar e used to g ene r a t e a n alar m at a sp ecific t i me an d ca len dar f i eld s ca n be inde pe nde nt ly mask ed f o r a l ar m co mpa r ison. t o gen er a t e a p e r i od ic int e r r upt , a 1 6 - b it p r o g r a m m ab le bin a r y au to -r elo ad d o wn co unt er wit h p r og r a mm ab le re so lut i on is a v aila b l e a n d a llo ws aut o m at ic w a k e u p and per io dic alar ms f r om e v er y 1 2 0 s t o e v er y 3 6 h our s . a 20 -bi t pr escaler is used f o r t he t i me ba se clo c k. it is b y d e f a u l t conf ig ure d t o gen er a t e a t i me b a se of 1 se co nd f r o m a cloc k a t 3 2 . 768 khz. th e ba c kup sram siz e is 4 kb yt es a n d ca n be e nab le d b y sof t w a r e . when th e ba c k u p ram is ena b l ed t he p o w e r con sump t io n in sta n d b y or v ba t mod e is sligh t ly high er ( see se ct ion 2 .2 . 19: lo w-p o w e r m ode s ). th e ba c k u p re gist ers ar e 32 -b it re gist er s used t o st or e 80 b yte s of user a p p lica t io n da ta when v dd po w e r is not pr esen t. ba c kup r egist er s ar e no t r e set b y a syst em, a po w e r re set , o r when t h e de vice w a k e s u p fr om t h e st an db y mo de ( s e e sect ion 2 . 2 .1 9: l o w- po w e r mo de s ). th e r tc , bac ku p ram an d ba c kup r e g i st er s ar e sup p lied th ro ug h a s wit ch th at t a k e s po w e r fr om e i th er th e v dd sup p ly whe n pr esen t or th e v ba t pin . 2.2.19 lo w-po wer modes th e stm3 2f2 05xx a n d stm 32f 207 xx supp or t t h r e e lo w- po w e r mod e s to a c h i e v e t h e b e st com p ro mise be tw een lo w po w e r con s u m pt ion , sho r t sta r tu p tim e and a v ail a b l e w a k e up sources: sle e p mode i n sleep m ode , only t he cpu is st op ped . all per iphe r a ls co nt in ue t o op er a t e and ca n w a k e up t h e cpu whe n an in te rr u p t / e v ent occur s . stop mode the sto p mo de achie v e s t h e lo w e st po w e r co nsump t io n while re ta ining t he con t e n t s of sram a nd r egist er s . all cloc ks in t h e 1 . 2 v d o ma in ar e st op pe d, t h e pl l, t h e hsi rc description stm32f205xx, stm32f207xx 24/147 doc id 15818 rev 5 and the hs e cr ystal osc illators are disab l ed. the v o ltage regulator can also be put either in nor m al or in lo w-po w e r mode . the de vice ca n b e w o k e n up f r om t he st op mo de b y an y of t h e exti line . the exti line sour ce ca n be o ne of t he 16 e x te r n a l lin es , t he pvd o u t put , t h e r t c ala r m / w a k e u p / t a mp er / tim e st am p e v en t s , t he usb o t g fs/hs w a k e up o r t he et her net w a k e up . sta ndb y mode the st a ndb y m ode is used t o a c h i e v e t he lo w e st po w e r con s u m pt ion . th e int e r nal v o lt ag e re gula t o r is s wit ch ed o f f so t h a t t h e e n t i re 1 . 2 v d o ma in is po w e r ed of f . th e pll, the hsi rc and the hse cr y s tal oscillators are also s witched off . after enter i ng sta n d b y mod e , t he sram and r e g i st er co nt en ts ar e lost e x cep t f o r r e g i st er s in th e ba c k u p do main a nd t h e b a c k up sram wh en sele ct e d . the de vice e x it s t h e sta ndb y mod e when an e x t e r nal r e set (nrst pin) , an i w dg r e set , a r i sing e dge o n t he wkup pin , or an r t c alar m / w a k eup / t a mp er / t i m e sta m p e v e n t occurs . not e : 1 th e r t c , t h e i w dg , and t he co rr espo nd ing clo c k so ur ce s ar e n o t st opp ed when t he de vice e n t e r s t he st op o r sta ndb y mod e . 2.2.20 v ba t operation th e v ba t pin a llo ws to p o w e r th e de vice v ba t d o m a in fro m a n e x ter n al ba tte r y o r an e x te r n al su pe rc ap a c ito r . v bat ope r a t i on i s act i v a t ed whe n v dd is no t pr es en t. not e : w he n t he micro cont r o ller is supp lied f r om v ba t , e xt e r n al int e r r up ts an d r t c ala r m/ e v e n t s d o not e xit it fr om v ba t ope r at i on . 2.2.21 timer s and watc hdogs th e stm3 2f2 05xx a n d stm 32f 207 xx de vices includ e t w o ad v anced -con t r ol t i mer s , eigh t gene r a l- pu r p ose t i m e r s , tw o b a sic t i me rs a n d t w o w a t c h d o g tim e r s . ta b l e 3 co mpa r e s t h e f e a t u r e s of t he ad v anced -con t r ol, ge ner al-p ur po se a nd b a sic timer s . t a b l e 3. ti mer f eat ure c o mpar is on timer type time r counter re solution coun ter type pre scaler factor dma reques t g e ne rati on capture / c o mpar e ch a n n e l s c o mple mentar y ou tpu t max interface cl o c k ma x timer cl o c k adv a nced- control tim 1 , ti m8 16 -b it up , do w n , up/do w n an y intege r betw e en 1 a nd 655 36 ye s 4 y e s 6 0 m h z 1 20 mhz gener a l pu r p ose tim 2 , ti m5 32 -b it up , do w n , up/do w n an y intege r betw e en 1 a nd 655 36 ye s 4 n o 3 0 m h z 60 mhz tim 3 , ti m4 16 -b it up , do w n , up/do w n an y intege r betw e en 1 a nd 655 36 ye s 4 n o 3 0 m h z 60 mhz basic tim 6 , ti m7 16 -b it up an y intege r betw e en 1 a nd 655 36 ye s 0 n o 3 0 m h z 60 mhz stm32f205xx, stm32f207xx description doc id 15818 rev 5 25/147 ad v a nced-contr o l timer s (tim1, tim8) th e ad v anced -con tr ol t i mer s ( t i m 1, ti m8) ca n be see n as t h ree - p hase pwm ge ner at or s m u ltip le x ed o n 6 ch an nels . th e y ha v e co mple men t a r y pwm o u t p u t s wit h p r og r a mm ab le in se r t e d dea d t i mes . the y ca n also be con sider ed a s comp let e ge ner al- pur po se t i me rs . th eir 4 inde pen de nt cha n n e ls can be used f o r : in p u t ca pt ur e ou tp ut co mpa r e pwm g e n e r a tio n (e dge - or ce nt er -a ligne d mod e s) on e- pulse mo de o u t put i f co nf igu r e d a s st an dar d 1 6 - b it t i mer s , t h e y ha v e t h e sa me f e at ur es as t h e gen er a l -p ur pose timx timers . if c o nfigured as 16-bit pw m gener a tors , the y ha v e full modulation capability (0- 1 00%) . th e ti m1 a nd ti m8 cou n t e r s can b e fr oz e n in de b u g mo de . ma n y of t he ad v anced -con t r ol t i me r f e at ur es ar e sh ar ed with th ose of th e st an da rd ti mx tim e r s which ha v e t he same a r chit ect u r e . the adv a n ced- cont r o l tim e r can t h ere f o r e w o r k to ge th er wit h th e ti mx t i me rs via th e t i me r lin k f e atu r e f o r sy nc hr on iza t io n or e v en t ch ain i ng . general-pu rpo se timer s (t imx) th er e ar e te n syn c h r o n izab le ge ner al- pur po se t i me rs emb edd ed in t h e stm 32f 20x de vices (s ee ta b l e 3 f o r diff erences). tim2, tim3, tim4, tim5 the stm32 f 20 x inclu de 4 f u ll- f e at ur ed g ene r a l- pu r p ose tim e r s . ti m2 a nd ti m5 a r e 3 2 - b it tim e rs , an d t i m 3 an d ti m 4 a r e 16 -b it t i m e r s . t h e t i m 2 a n d t i m 5 tim e rs ar e b a s e d o n a 32 -b it au to -r elo a d u p / d o wn co un te r an d a 32 -b it pr es cale r . t h e t i m 3 a n d ti m4 t i mer s a r e b a sed o n a 16 -bit au to -r elo ad up /d o w n coun te r an d a 16 -b it pr escaler . the y all f e at ur e 4 ind epe nd ent ch an nels f o r inp u t ca pt ur e/ out p u t com par e , pwm or on e- pulse mo de o u t put . t h is g i v e s up t o 16 in put ca pt ur e/ ou tp ut co mpa r e/ pwms o n t he lar g e s t pa c k a ges . gener a l pu r p ose tim9 16-b i t u p an y intege r betw e en 1 a nd 655 36 no 2 no 6 0 m hz 1 20 mhz tim10, ti m11 16-b i t u p an y intege r betw e en 1 a nd 655 36 no 1 no 6 0 m hz 1 20 mhz tim12 16-b i t u p an y intege r betw e en 1 a nd 655 36 no 2 no 3 0 m hz 60 mhz tim13, ti m14 16-b i t u p an y intege r betw e en 1 a nd 655 36 no 1 no 3 0 m hz 60 mhz t a b l e 3. timer f eat ure c o mpar is on (c ont in ue d) timer type time r counter re solution coun ter type pre scaler factor dma reques t g e ne rati on capture / c o mpar e ch a n n e l s c o mple mentar y ou tpu t max interface cl o c k ma x timer cl o c k description stm32f205xx, stm32f207xx 26/147 doc id 15818 rev 5 th e ti m2 , ti m3 , ti m4 , ti m 5 ge ne r a l- pu r p o s e tim e rs ca n w o r k t o g e th e r , o r w i th th e ot he r ge ner al- pur po se t i me rs and th e adv a n ced - con t r o l t i mer s ti m1 a nd ti m8 via t h e t i m e r l i nk f e at ur e f o r s y n c h r on iza t ion or e v en t chain i ng . the co unt er s o f ti m2 , ti m3 , ti m4 , ti m5 can b e fr oz en in de b ug mo de . an y o f t h e s e ge ner al- pur po se t i me rs ca n be u s e d to gen er a t e pwm ou tp ut s . tim 2 , tim 3 , tim 4 , tim 5 a ll h a v e in de pe n d e n t dm a re qu e st ge ne r a t i on . th e y ar e capa b l e of h and ling q uad r a t u r e ( i ncre men t a l ) en co de r sig n a l s an d t he dig i t a l out pu t s f r om 1 t o 4 h a ll- ef f e ct sensor s . tim10 , tim1 1 and t i m9 the se tim e r s ar e ba se d on a 1 6 - b it a u t o - r e l oad upcou nt er a n d a 1 6 - b it p r e s cale r . ti m10 a n d t i m1 1 f eat ur e on e ind epe nd ent ch an nel, wh er eas ti m9 ha s t w o ind epe nd ent ch an nels f o r inp u t ca pt ur e/ out p u t com par e , pwm or o ne- pu lse mod e ou tp ut . th e y can be synchr o n i z e d wit h t he ti m2 , ti m3, ti m4, ti m5 f u ll- f e at ur ed ge ner al- pur po se t i me rs . the y ca n also be u s e d as sim p le t i me ba ses . tim12 , tim1 3 and t i m1 4 the se tim e r s ar e ba se d on a 1 6 - b it a u t o - r e l oad upcou nt er a n d a 1 6 - b it p r e s cale r . ti m13 a n d t i m1 4 f eat ur e on e ind epe nd ent ch an nel, wh er eas ti m12 h a s tw o ind epe nd ent ch an nels f o r inp u t ca pt ur e/ out p u t com par e , pwm or o ne- pu lse mod e ou tp ut . th e y can be synchr o n i z e d wit h t he ti m2 , ti m3, ti m4, ti m5 f u ll- f e at ur ed ge ner al- pur po se t i me rs . the y ca n also be u s e d as sim p le t i me b a ses . 2.2.22 basic time r s tim6 and tim7 th ese t i mer s a r e ma inly used f o r d a c t r igg e r a nd w a v e f o r m gen er a t io n. the y can a l so be u s e d as a gen er ic 16- bit tim e base . 2.2.23 independent watc hdog th e ind epe nd ent w a t chdo g is b a sed o n a 12 -bit do wncou n t e r a n d 8 - b i t pr escaler . it is cloc k e d f r o m an inde pe nde nt 32 khz int e r n al rc a n d as it o per at es inde pe nde nt ly fr om t h e ma in cloc k, it can ope r a t e in sto p an d st and b y mo de s . i t ca n be used eit her as a w a t c h dog t o r e set t he d e vice when a pr ob lem occu rs , o r as a f r ee- r u n n in g t i mer f o r a pplica t io n t i meo u t ma na gem ent . i t is ha rd w a r e - o r sof t w a r e -co n f i gur ab le th ro ug h th e opt io n b yt e s . th e coun te r can b e fr oz e n in de b u g mo de . 2.2.24 windo w watc hdog th e windo w w a t chdo g is b a sed o n a 7- bit d o wn c oun te r t hat can be se t as fr ee -r u nnin g . it can be u s e d as a w a tch dog to rese t t h e d e vice when a pr ob lem o ccu rs . i t is cloc k e d fr om t h e main cloc k. it has an ear l y w a r n ing interr up t capability and the counter c a n be froz en in d e b ug mo de . stm32f205xx, stm32f207xx description doc id 15818 rev 5 27/147 2.2.25 systic k timer th is t i me r is d e d i ca te d t o re al- t ime ope r a t i ng syste m s , b u t cou l d also be used a s a st and ar d d o wn co unt e r . it f eat ur es: a 2 4 - b it do wncoun te r a u toreload capability m a s ka b le sys te m int e r r up t ge ne r a t i on w h e n th e co un te r r e ach e s 0 pro g r a m m ab le cloc k so ur ce 2.2.26 i2c b u s up t o th re e i 2 c b u s int e r f aces ca n ope r a t e in m u ltim aste r an d sla v e mo des . th e y ca n sup por t t h e sta nda rd - a nd f a st -m ode s . the y supp or t t he 7 / 10- bit ad dr essin g m ode an d t h e 7- bit d u a l a d d r ess i ng m o de ( a s sla v e) . a ha rd w a r e crc g e n e r a tio n / v er if ica t io n is e m be dde d. th e y can be se r v ed b y dm a a nd t h e y sup por t smbus 2 . 0/ pm bus . 2.2.27 univer sal sync hr onous/ async h r onous receiver transmitter s (u ar ts/usar t s) th e stm3 2f2 05xx a n d stm 32f 207 xx em bed f o u r un iv er sa l synchr o n ous/ a synchro no us re ce iv er t r a n sm i tte rs (u sar t1 , u sar t2, usa r t3 a n d usar t6 ) an d two un iv e r sa l as yn chr o no us r e ce iv e r tr an sm it te rs (u ar t4 and u a r t 5) . th ese six in te rf aces pr o vid e asyn chro no us co mm u n i ca tion , ird a s i r e ndec su pp o r t, m u ltip ro ce ssor co mm un ica t io n mo de , sing le- w ir e ha lf- d u p le x comm un icat ion mo de a nd ha v e lin master/sla v e capability . the usar t1 and u sar t6 interf aces are ab le to com m u nicat e at spee ds o f u p to 7 . 5 mbit / s . th e ot he r a v ailab l e in te rf aces co mm un ica t e at up t o 3.7 5 m b it /s . usar t 1 , usar t2 , usar t3 an d usar t6 also p r o vide ha rd w a r e m ana gem ent o f t he ct s an d r t s s i gn a l s , sm ar t ca r d m o de ( i so 7 8 1 6 co m p lia nt ) an d spi- lik e co mm u n i cat i on ca pa b i lit y . all in te rf ac es ca n be s e r v ed b y t h e dm a con t r o lle r . t a b l e 4. usar t f e a t ure compa r i s on usar t name st andar d featur es modem (r ts/ c ts) lin spi ma ster ird a smar tcar d (iso 7 816 ) max . ba ud ra te in mb it/ s (o ver s a mpling by 1 6 ) max. baud rate in mb it/ s (o ve r s am p lin g by 8 ) apb mapping u s ar t1 x x x x x x 3.75 7 . 5 apb2 (m ax . 60 mhz) u s ar t2 x x x x x x 1.87 3.75 apb1 (m ax . 30 mhz) u s ar t3 x x x x x x 1.87 3.75 apb1 (m ax . 30 mhz) description stm32f205xx, stm32f207xx 28/147 doc id 15818 rev 5 2.2.28 serial perip heral interface (spi) th e stm3 2f2 0 x f e a t ure up t o th re e spis in sla v e an d ma st er mod e s in f u ll-du ple x an d simple x comm unication modes . s p i1 ca n co mm u n i ca te at u p to 30 m b its/ s , spi 2 an d spi3 can com m unicat e a t up t o 1 5 mbit / s . t he 3- bit pr esca ler g i v e s 8 m a ste r mo de f r e q u encies an d th e f r a m e is co nf igu r ab le to 8 b i ts o r 16 bit s . t h e ha r d w a re cr c ge ne r a t i on /v e r ific at ion sup por t s b a sic sd ca rd /m mc mo de s . all spis ca n be ser v ed b y t h e dma cont r o lle r . th e spi int e rf ace can be co nf igur ed t o o per at e in ti m ode f o r co mm un ica t ions in mast er mo de a nd sla v e mod e . 2.2.29 inter - integrated sound (i 2 s) t w o sta nda rd i 2 s int e r f a c e s ( m ult i ple x e d wit h spi 2 and spi 3 ) are a v a ilab l e . th e y ca n be o per at ed in ma ste r or sla v e mod e , an d can be co nf igur ed t o o per a t e wit h a 1 6 - / 3 2 -b it r e solu tio n as in pu t or o u t p u t chan ne ls . a u d i o sa mplin g fr eq ue ncies f r om 8 khz up t o 96 khz ar e su pp o r te d. wh en e i th er o r bo th o f t h e i 2 s int e r f aces is/ a r e conf ig ure d in ma st er mod e , t h e m a ste r cloc k ca n be o u t put to th e e x te r n al d a c/codec a t 2 56 t i mes t he samp ling fr eq ue n c y . 2.2.30 sdio an sd/s dio/mmc hos t interf ac e i s a v ailab l e , th at su pp o r ts mu ltimediacard sy stem sp ecificat io n v e r s io n 4. 2 in t h r ee d i ff er en t da ta b u s m ode s: 1- bit ( d e f a u lt ), 4- bit and 8 - b i t. th e int e r f ace allo ws d a t a tr ansf e r a t up to 4 8 mhz in 8 - b i t mo de , a nd is co mplia nt wit h th e sd memo r y ca rd sp ecifi c a t io n v e r sion 2. 0 . th e sdio car d spe c if icat ion v e rsio n 2. 0 is a l so sup p o r t e d wit h t w o d i ff er en t da t a b u s mo de s: 1- bit ( d e f a u lt ) an d 4- bit . th e cur r en t v e r sion sup por t s o n ly one sd/ s di o/ mm c4 .2 car d at an y one t i me a nd a st ac k of m m c4. 1 or p r e vio us . i n ad dit i on t o sd/ s dio / m m c , th is in te rf ace is f u lly co mplia nt wit h th e ce- a t a d i git a l pr ot ocol re v1.1. u ar t 4 x - x - x - 1 .87 3 .75 apb1 (m ax . 30 mhz) u a r t 5 x - x d - x - 3.75 3.75 apb1 (m ax . 30 mhz) u s ar t6 x x x x x x 3.75 7 . 5 apb2 (m ax . 60 mhz) t a b l e 4. usar t f e a t ure compa r ison ( c ont in u e d) usar t name st andar d featur es modem (r ts/ c ts) lin spi ma ster ird a smar tcar d (iso 7 816 ) max . ba ud ra te in mb it/ s (o ver s a mpling by 1 6 ) max. baud rate in mb it/ s (o ve r s am p lin g by 8 ) apb mapping stm32f205xx, stm32f207xx description doc id 15818 rev 5 29/147 2.2.31 ethernet ma c interface with dedicated dma and ieee 1588 suppor t p e r i ph er a l a v aila b l e o n ly on t h e stm 32f 207 xx de vices . the stm32f207xx de vices pro v id e an ieee-802.3-2002-complia nt media access controller (m a c ) f o r et he r n e t lan co m m un ica t io ns th ro u g h a n ind u s t r y-s ta nd ar d m e d i um - in dep en den t int e rf ace (m ii ) o r a re du ce d med i um- i nd epe nd ent int e r f a ce (rmi i) . t he stm 32f 207 xx re qui res an e x t e r n a l p h ysica l in te rf ace de vice ( p hy) to con n e c t to t h e p h ysica l l a n b u s ( t wist ed -pa i r , f i be r , et c.) . t h e phy is conn ect ed t o th e stm3 2f2 07xx m i i p o r t u s in g 17 sign als f o r mi i o r 9 signa ls f o r rmi i , an d can be clo c k ed u s in g th e 25 mhz ( m i i ) or 5 0 mhz ( r m i i ) ou t put fr om t h e stm 32f 207 xx. th e stm3 2f2 07xx i n clude s t h e f o llo wing f e at ur es: sup por t s 1 0 and 100 m b it /s r a t e s dedicat e d dma co nt ro ller a llo win g h i gh -spe ed t r ansf e r s be tw ee n t h e d edica te d sram an d th e de scr i pt o r s ( see t h e stm 32f 20x an d stm32 f 21 x ref e r ence ma n u a l f o r details ) t a gg ed m a c fr am e su p p o r t (vl a n su pp or t) half -d uple x ( c sm a/ cd) an d fu ll-d uple x o per at ion m a c con t r o l su b l a y er (c on tr ol fr am e s) su pp o r t 32 -b it crc ge ner at ion an d re mo v a l se v e r a l ad dr ess filt er in g mo de s f o r ph ysical a n d m u lt ica s t a ddr ess (m ult i cast and g r o u p ad dr esse s) 32 -b it sta t u s cod e f o r ea ch tr a n smit t ed or re ce iv ed f r ame in te r n a l fifos to b u ff e r tr an sm it a n d r e c e iv e fr a m es . th e tr an sm it fifo a n d th e r e ceiv e fi fo ar e bo t h 2 kb yt es , th at i s 4 kb yt es in t o t a l suppor ts hardw a re ptp (pre cision time protocol) in accordance with ieee 1588 2008 ( p tp v2 ) w i th th e tim e sta m p co mp a r a t o r co nn ec te d to th e ti m 2 in p u t t r ig ger s in te rr u p t whe n syst em t i me be come s g r eat er th an t a r get t i me 2.2.32 contr o ller area netw o rk (can) th e tw o cans ar e co mplia nt with t h e 2. 0a and b ( a ct iv e) specif ica t ions wit h a b i tr at e u p to 1 mb it /s . the y ca n re ce iv e and tr a n smit st an dar d f r am es wit h 11 -bit ide n t i fie r s as w e ll as e x t e n d e d f r am es wi th 29- bit id ent if ier s . each can has t h r e e tr ansmit ma ilbo x e s , tw o r e ceiv e fi fo s wit h 3 st age s a nd 2 8 sh ar ed scala b l e f ilt er ban ks (a ll of t h em can b e used e v en if on e can is used ). t he 2 56 b y t e s of sram which ar e allo ca t ed f o r e a ch can ar e no t shar ed wit h an y o t h e r p e r i p her al. 2.2.33 univer sal se rial b u s on-the-go full-speed (o tg_fs) th e stm3 2f2 05xx a n d stm 32f 207 xx e m bed an usb o t g f u ll- spee d d e vice/ h ost/ o t g p e r i ph er a l wit h int e g r at ed t r an sce i v e rs . th e usb o t g f s pe r i ph er a l is co mplia nt wit h t h e usb 2 . 0 sp ecifica t io n and wit h t h e o t g 1. 0 specif ica t io n. it has sof t w a re -con fig u r a b l e e ndp oin t set t in g an d su pp or ts suspen d/ re sume . t he usb o t g fu ll-spe ed con t r o lle r description stm32f205xx, stm32f207xx 30/147 doc id 15818 rev 5 r e q u ire s a d edica te d 48 mhz clo c k t h a t is g ene r a t e d b y a pll con nect ed t o t he hse os cillator . the major f e atures are: comb ined rx and t x fi fo siz e o f 32 0 3 5 bit s wit h dyna mic fi fo sizing sup por t s t h e session r e q uest pro t o c ol (srp) an d ho st neg ot iat i on p r o t o c o l (hnp) 4 bid i re ct ion a l en dpo int s 8 ho st chan nels with p e r i o d ic o u t sup p o r t hnp/ snp/ i p in side ( no ne ed f o r a n y e x t e r nal r e sist o r ) f o r o tg/ host m ode s , a p o w e r s wit ch i s ne ede d in case b u s-p o w e r ed d e vice s a r e conn ect e d in te r n a l fs o t g phy su pp o r t ext e r na l f s o t g phy su pp or t t hr ou gh an i 2 c co nne ct io n 2.2.34 univer sal se rial b u s on-the-go high-speed (o tg_hs) th e stm3 2f2 05xx a n d stm 32f 207 xx de vices emb e d a usb o t g hig h - s p eed (up to 4 8 0 m b / s) d e vice / host / o t g pe r i phe r a l. the usb o t g hs sup por t s b o t h f u ll- sp eed and h i gh- spee d op er a t io ns . it int e g r a t e s t h e t r a n sce i v e r s f o r f u ll- spee d op er a t io n (1 2 m b/ s) a n d f e a t u r e s a utmi lo w- pin in te rf ace ( u l p i) f o r hig h - s p eed ope r a t i on ( 4 8 0 mb/ s ) . whe n using t h e usb o t g hs in hs mod e , an e x t e r n a l ph y de vice conn ecte d t o th e ulpi is re quir e d . the usb o t g hs per i pher a l is compliant with the usb 2.0 sp ec if ica t io n an d with t h e o t g 1 . 0 spe cificat ion . i t h a s so ft w a re- conf ig ur ab le e ndp oin t set t in g an d su pp or t s su sp en d/ re su m e . t h e usb o t g fu ll-s p e e d c o n t r o lle r re qu ir es a de d i cat e d 4 8 m h z c l oc k that is gener a ted b y a pll connected to the hse osc illato r . the major f eatures are: co m b in e d rx a n d tx f i f o siz e of 1 kb it 35 w i th dy na m i c f i f o siz i ng sup por t s t h e session r e q uest pro t o col (srp) an d ho st neg ot iat i on p r o t o c o l (hnp) 6 bid i re ct ion a l en dpo int s 12 h o st cha nne ls wit h per iodic out su pp or t in te r n a l fs o t g phy su pp o r t ext e r na l f s o t g phy su pp or t t hr ou gh an i 2 c co nne ct i o n ext e r n a l hs o r hs o tg op er a t io n supp or t i ng ulpi i n sdr mod e . t he ot g phy is co n n e cte d to t h e m i cr oc on tr olle r ulp i p o r t t h r o ug h 12 s i gn als . i t ca n b e cloc ke d us in g t he 60 m h z ou tp ut . in te r n a l us b dm a hnp/ snp/ i p in side ( no ne ed f o r a n y e xt e r nal r e sist o r ) f o r o t g / h o s t mod e s , a po w e r s w it ch is n e e ded in ca se b u s- po w e re d de vices ar e conn ect e d 2.2.35 a udio pll (plli2s) th e de vices f eat ur e an a d d i tio nal d edicat e d pl l f o r a udio i 2 s applic ation. it allo ws to ac hie v e e r r o r - fr ee i 2 s sa mpli ng cloc k accu r a cy wit ho ut com p r o mising o n t he cpu p e r f o r ma nce , while u s in g usb pe r i phe r a ls . th e pll i 2 s con f ig ur a t io n can be m odi fie d to m ana ge a n i 2 s samp le r a t e chan ge wit ho ut d i sa b lin g t he ma in pll ( p ll) u sed f o r cpu , usb an d eth e r n et int e r f a c e s . th e au dio pll ca n be pr og r a mme d with v e r y lo w er ro r t o obt a i n sa mplin g r a t e s r a n g in g fr om 8 k h z to 9 6 khz . stm32f205xx, stm32f207xx description doc id 15818 rev 5 31/147 i n ad dit i on t o t h e a udio pl l, a mast er cloc k inpu t p i n ca n be u s e d t o synch r on iz e t h e i 2 s f l o w wit h an e x t e r nal pll (or co de c ou tp ut ). 2.2.36 digital came ra interface (dcmi) th e came r a int e r f ace is no t a v aila b l e in st m32 f 20 5xx de vice s . stm 32f 207 xx pr odu cts emb ed a cam e r a in te rf ace t hat can conn ect wit h came r a mod u le s an d cm o s se n sor s t h r o ug h an 8 - b i t to 14 -b it pa r a lle l in te rf ace , t o r e ceiv e v i de o d a ta . t h e cam e r a in te rf ace can sust ain u p to 2 7 mb yt e / s at 2 7 mhz o r 48 m b yt e/ s at 48 m h z. i t f e at ur es : pro g r a m m ab le po lar i t y f o r th e inpu t p i x e l clo c k an d syn c h r o n izat ion sign als p a r a lle l dat a comm u n icat ion can b e 8- , 1 0 -, 12 - or 1 4 - b it sup por t s 8 - b i t pr og r e ssiv e vid eo mo no ch ro me or r a w ba y e r f o r m at , ycbcr 4 : 2 : 2 pr og r e ssiv e vid e o , rg b 5 65 pr og r e ssiv e vid eo o r co mpr e ssed d a t a (lik e jpeg) sup por t s con t in u o u s mo de or sn ap sh ot ( a single fr a m e) mod e capability to automati cally c r op the image 2.2.37 gpios (g enera l-purpose inputs/outputs) ea ch o f t he g p i o p i ns ca n be con f ig ur ed b y sof t w ar e as out pu t ( push - pu ll or o pen -d r a in , wit h or wit ho ut p u ll- up or pull- do wn) , a s inp u t (f loating, with or w i thou t pull-up or pull-do wn) o r as per ip he r a l alt e r nat e f u n c t i on . mo st of th e gpi o pin s ar e sha r ed wit h dig i ta l or a nalo g a l te r n a t e fu nctio n s . all g p io s a r e h i gh- curr en t- capa b l e and h a v e sp eed se lectio n to bet t e r ma na ge int e r n a l n o ise , po w e r con sump t io n and elect r o m ag net ic e m ission. th e i / o a l te r n at e fu nct i on con f ig ur a t io n ca n be lo c k e d if nee de d b y f o llo win g a specif ic seq uen ce in or der to a v oid sp ur iou s wr it ing t o th e i / o s r egist er s . t o pro v ide f a st i/ o ha nd ling, t he gpi o s ar e on t h e f a st ahb1 b u s wit h a cloc k up t o 1 2 0 m hz t h at le ads t o a maxim u m i / o to gg ling spee d of 60 mhz. 2.2.38 adcs ( analog-to-digital con ver ter s ) th re e 12 -bi t an alog -t o- dig i ta l co n v e r t e rs a r e e m be dd ed an d ea ch adc sha r e s u p to 1 6 e x te r n al ch an n e ls , pe rf or m i ng co n v e r sion s in the s i ng le -sh o t o r sca n mo d e . i n sca n m o d e , a u t o ma tic con v e r sion is pe rf or med o n a select ed g r ou p of a n a l og inp u t s . ad dit i ona l lo gic fu nct i ons emb edd ed in t h e adc int e r f a c e a llo w: sim u lt an eou s samp le an d hol d i n t e r l ea v e d sa mple a nd h o ld th e adc can be se r v ed b y th e dm a con t r o lle r . an an alo g w a t chdo g f eat ur e allo ws v e r y p r e c ise mo nit o r i n g of t h e co n v e r t e d v o lt age o f o n e , some or a ll sele ct e d ch ann els . an in te rr u p t is ge ner at ed whe n th e co n v e r te d v o lt ag e is ou tsid e th e pr og r a mme d th re sh olds . the e v en ts g e n e r a te d b y th e tim e r s tim 1 , tim 2 , ti m3 , ti m4 , ti m5 a n d ti m8 c a n b e int e r n ally co nn e cte d to th e adc sta r t tr ig ge r an d injection tr igger , res p e ctiv e ly , to a llo w th e applicat ion t o synchroniz e a/ d con v ersion and timers . description stm32f205xx, stm32f207xx 32/147 doc id 15818 rev 5 2.2.39 d a c (digital-t o-analog con ver ter) th e t w o 12 -b it b u f f er ed d a c ch an nels ca n be u s e d t o co n v e r t t w o dig i t a l sig n a l s int o t w o a nalo g v o lt ag e sig n a l o u t put s . the d e sign st r u ct ure is comp osed o f int e g r at ed r e sisto r st r i ngs an d an a m plif ier in in v e r t in g co nf igu r at ion . th is d ual di git a l in te rf ace sup por t s t h e f o llo win g f e at ur es: t w o d a c co n v e r te rs: o ne f o r e a ch ou tp ut ch ann el 8- bit or 1 2 -b it mo no to nic o u t p u t le ft or r i g h t da ta a lig nm e n t in 12 -b it mo d e sy nc hroniz ed update capability no ise - w a v e g ene r a t i on tr ia n g u l ar -w a v e ge ne r a t i on du al d a c ch ann el ind epe nde nt or sim u lt an eou s con v er si ons dma capability f o r each c h annel e x t e r n al t r igge rs f o r con v er sio n in pu t v o lt ag e re f e re n c e v ref+ eig h t d a c t r igge r inp u t s a r e u s e d in t he de vice . the d a c chan ne ls ar e t r igge re d th ro ug h t h e t i me r up dat e o u t put s th at a r e a l so co nne ct e d to d i ff er en t dma st r eam s . 2.2.40 t e mperature sensor th e t e m per at ur e sen s o r h a s t o ge ne r a t e a v o lt age t hat v a r i es line a r l y wi th te mpe r at ur e . the con v er sion r a nge is be tw een 1. 8 v a nd 3. 6 v . t he t e mp er a t u r e sen s o r is in t e r n ally con nect e d t o t h e adc1_i n16 in put ch an nel which is u s e d t o co n v e r t t he sen s o r ou tp ut v o l t age into a digital v a lue . as th e of f s e t o f t he t e mp er a t ure se nsor v a r i es fr om chip t o chip due t o p r o c e s s v a r i a t io n, t h e in te r n a l te mpe r at ur e sensor is ma inly su ita b le f o r ap plicat ions t hat det e c t te mpe r at ur e cha nge s in st ea d of absol ut e te mpe r at ur es . i f an a c cu r a t e t e mp er a t u r e r ead ing is ne ede d, t h e n an e x t e r nal t e m per a t ure se nsor p a r t sho u ld b e used . 2.2.41 serial wire jt a g deb ug por t (swj-dp) th e arm swj-dp int e r f a c e is em bed ded , a nd is a co mbin ed jt a g an d se r i al wire d e b u g p o r t t h a t en ab les eit h e r a ser i al wire d e b u g o r a jt a g pr ob e to b e conn ect ed t o th e t a rg et . t h e jt a g t m s a n d t c k pin s ar e sh ar ed wit h swdi o an d swcl k, re sp ec tiv e ly , a n d a spe c if ic se que nce on t h e tms pin is u s ed t o s wit ch bet w een jt a g -dp a n d sw -dp . 2.2.42 embed ded t r ace macr ocell? the arm embedded t r ace ma c r ocell pro v ides a g r eater visib ility of the instr u ction and data f l o w in sid e t he cpu cor e b y str eam ing com p re sse d dat a a t a v e r y h i gh r a te f r om t he stm 32f 20x th ro ugh a sm all n u mb er o f etm pin s t o an e x te r n a l h a r d w a re t r a c e p o r t a nalyz e r (t p a ) de vice . th e tp a is conn ecte d t o a ho st co mpu t e r using usb , eth e r n et , o r a n y ot he r hig h - s p eed ch ann el. re al- t im e instr u ctio n and dat a f l o w act i vity ca n be r e cor d e d a nd t h e n f o r m a t t e d f o r displa y on t h e host co mpu t e r t hat r uns t he de b u gg er sof t w ar e . tp a h a r d w a re is co mmer cially a v a ilab l e fr om com m on d e v e lo pme n t t o ol v e nd or s . the embedded trace macrocell operates with third party debugger software tools. stm32f205xx, stm32f207xx pinouts and pin description doc id 15818 rev 5 33/147 3 pinouts and pin description fi gu re 9. stm 32f 20x l q fp6 4 pi nou t fi gu re 10 . s tm 32f 20x wlcsp6 4 + 2 bal l o ut 1. to p view. 64 63 6 2 6 1 60 59 5 8 5 7 56 55 5 4 5 3 52 51 5 0 4 9 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 1 7 18 1 9 20 2 1 22 2 3 24 29 3 0 31 3 2 2 5 26 27 2 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 6 " ! 4 0 # / 3 # ? ) . 0 # / 3 # ? / 5 4 . 2 3 4 0 # 0 # 0 # 0 # 6 3 3 ! 6 $ $ ! 0 ! 7 + 5 0 0 ! 0 ! 6 $ $ ? 6 3 3 ? 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 # 0 # 0 # 0 ! 0 ! 6 $ $ ? 6 # ! 0 ? 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 " 0 " 0 " 0 " 0 ! 6 3 3 ? 6 $ $ ? 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 " 0 " 6 # ! 0 ? 6 $ $ ? , 1 & 0 a i b 0 # 2 4 # ? ! & 0 ( / 3 # ? ) . 0 ( / 3 # ? / 5 4 ! 0 ! 0 ! 0 # 0 " 0 " 0 " 0 " 6 $ $ ? " 0 ! 0 # 0 " 0 " " / / 4 0 " 0 # # 0 ! 6 # ! 0 ? 0 # 0 $ 0 $ 2 / & & $ 0 # 0 ! 0 ! 0 # % 0 ! 0 ! & 0 # 0 # ' 0 " 0 # 0 # 0 ! 0 # ( 0 " 0 " 0 " 0 # * 0 " 0 " 6 # ! 0 ? 0 " 0 " 0 ! 0 ! a i 6 " ! 4 6 3 3 ? 0 # 0 # 6 3 3 ? 6 $ $ ? 6 $ $ ? 0 ! . 2 3 4 0 ( / 3 # ? ) . 6 3 3 ? 6 2 % & 0 # 0 ( / 3 # ? / 5 4 0 # 0 ! 0 ! 2 % ' / & & 0 ! 6 3 3 ? 0 " 0 ! pinouts and pin description stm32f205xx, stm32f207xx 34/147 doc id 15818 rev 5 fi gu re 11 . s tm 32f 20x l q fp1 00 pi nou t 1. rfu means ?reserve d for future use?. 0 % 0 % 0 % 0 % 0 % 6 " ! 4 0 # / 3 # ? ) . 0 # / 3 # ? / 5 4 6 3 3 ? 6 $ $ ? 0 ( / 3 # ? ) . . 2 3 4 0 # 0 # 0 # 0 # 6 $ $ ? 6 3 3 ! 6 2 % & 6 $ $ ! 0 ! 7 + 5 0 0 ! 0 ! 6 $ $ ? 6 3 3 ? 6 # ! 0 ? 0 ! 0 ! 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 # 0 # 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 " 0 " 0 " 0 " 0 ! 6 3 3 ? 6 $ $ ? 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 ? 6 $ $ ? 2 & 5 6 $ $ ? 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! a i d , 1 & 0 0 # 2 4 # ? ! & 0 ( / 3 # ? / 5 4 stm32f205xx, stm32f207xx pinouts and pin description doc id 15818 rev 5 35/147 fi gu re 12 . s tm 32f 20x l q fp1 44 pi nou t 1. rf u means ?rese r ved for fut ure use?. 2 & 5 6 $ $ ? 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 ' 6 $ $ ? 6 3 3 ? 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 $ 0 $ 6 $ $ ? 6 3 3 ? 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ! 0 ! 0 % 6 $ $ ? 0 % 6 3 3 ? 0 % 0 % 0 ! 0 % 0 ! 6 " ! 4 0 ! 0 # 2 4 # ? ! & 0 ! 0 # / 3 # ? ) . 0 ! 0 # / 3 # ? / 5 4 0 ! 0 & 0 # 0 & 0 # 0 & 0 # 0 & 0 # 0 & 6 $ $ ? 0 & 6 3 3 ? 6 3 3 ? 0 ' 6 $ $ ? 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 ( / 3 # ? ) . 0 $ 0 ( / 3 # ? / 5 4 0 $ . 2 3 4 6 $ $ ? 0 # 6 3 3 ? 0 # 0 $ 0 # 0 $ 0 # 0 $ 6 3 3 ! 0 $ 6 $ $ ? 0 $ 6 2 % & 0 $ 6 $ $ ! 0 " 0 ! 7 + 5 0 0 " 0 ! 0 " 0 ! 0 " 0 ! 6 3 3 ? 6 $ $ ? 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 & 0 & 6 3 3 ? 6 $ $ ? 0 & 0 & 0 & 0 ' 0 ' 0 % 0 % 0 % 6 3 3 ? 6 $ $ ? 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 ? 6 $ $ ? , 1 & 0 a i d 6 # ! 0 ? pinouts and pin description stm32f205xx, stm32f207xx 36/147 doc id 15818 rev 5 fi gu re 13 . s tm 32f 20x l q fp1 76 pi nou t 1. packag e not in production and available for developme n t only. 2. rf u means ?rese r ved for fut ure use?. 2 & 5 6 $ $ ? 0 % 0 % 0 " 0 " " / / 4 0 " 0 " 0 " 0 " 0 " 0 ' 6 $ $ ? 6 3 3 ? 0 ' 0 ' 0 ' 0 ' 0 ' 0 ' 0 $ 0 $ 6 $ $ ? 6 3 3 ? 0 $ 0 $ 0 $ 0 $ 0 $ 0 $ 0 # 0 # 0 # 0 ) 0 ) 0 % 6 $ $ ? 0 % 6 3 3 ? 0 % 0 % 0 ! 0 % 0 ! 6 " ! 4 0 ! 0 ) 2 4 # ? ! & 0 ! 0 # / 3 # ? ) . 0 ! 0 # / 3 # ? / 5 4 0 ! 0 & 0 # 0 & 0 # 0 & 0 # 0 & 0 # 0 & 6 $ $ ? 0 & 6 3 3 ? 6 3 3 ? 0 ' 6 $ $ ? 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 & 0 ' 0 ( / 3 # ? ) . 0 $ 0 ( / 3 # ? / 5 4 0 $ . 2 3 4 6 $ $ ? 0 # 6 3 3 ? 0 # 0 $ 0 # 0 $ 0 # 0 $ 6 3 3 ! 0 $ 6 $ $ ? 0 $ 6 2 % & 0 $ 6 $ $ ! 0 " 0 ! 7 + 5 0 0 " 0 ! 0 " 0 ! 0 " 0 ! 6 3 3 ? 6 $ $ ? 0 ! 0 ! 0 ! 0 ! 0 # 0 # 0 " 0 " 0 " 0 & 0 & 6 3 3 ? 6 $ $ ? 0 & 0 & 0 & 0 ' 0 ' 0 % 0 % 0 % 6 3 3 ? 6 $ $ ? 0 % 0 % 0 % 0 % 0 % 0 % 0 " 0 " 6 # ! 0 ? 6 $ $ ? , 1 & 0 a i d 6 # ! 0 ? 0 ) 0 ! 0 ! 6 $ $ ? 6 3 3 ? 0 ) 0 ) 0 ) 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ( 0 ) 0 ) 0 ( 0 ( 0 ( 6 $ $ ? 6 3 3 ? 0 ( 0 # 2 4 # ? ! & 0 ) 0 ) 0 ) 6 3 3 ? 6 $ $ ? 0 ( 0 ( stm32f205xx, stm32f207xx pinouts and pin description doc id 15818 rev 5 37/147 fi gu re 14 . s tm 32f 21x xx ufbga17 6 bal l out 1. rf u means ?rese r ved for fut ure use?. 2. to p view. 1 2 3 9 10 11 12 13 14 15 a p e 3 p e 2 pe 1 p e 0 p b 8 p b 5 p g14 p g13 pb 4 p b 3 p d7 p c 12 p a 15 p a 14 p a 13 b p e4 pe5 pe 6 pb9 p b7 pb6 p g 1 5 p g 12 p g 1 1 p g 1 0 p d 6 p d 0 p c 1 1 p c 1 0 p a1 2 cv ba t p i 7 p i 6 p i 5 rfu vd d_ 3 vd d _1 1 vd d _1 0 vd d_ 1 5 pg 9 pd 5 p d 1 p i3 p i 2 p a1 1 d p c 13- ta m p 1 pi 8 - ta m p 2 p i 9 p i 4 b o o t 0 v s s _11 v s s _10 v s s _15 p d4 p d 3 p d2 p h 15 p i 1 p a 1 0 e p c 14- o s c32_i n pf 0 p i1 0 p i1 1 p h 1 3 ph 1 4 pi 0 p a 9 f p c 15- os c3 2_ ou t vs s_ 1 3 vd d _ 1 3 p h 2 vs s vs s v s s vs s v s s v ss _ 2 v c a p2 pc 9 p a 8 g ph 0 - os c _ i n vs s_ 5 vd d _ 5 p h 3 vs s vs s v s s vs s v s s v ss _ 9 vd d _ 2 pc 8 pc 7 h ph 1 - os c _ o u t p f 2 p f 1 ph 4 v ss v s s v ss v ss v ss vs s _1 4 v d d _ 9 p g 8 p c 6 j nr s t p f 3 p f 4 ph 5 v ss v ss v ss v s s v ss vd d _1 4 v d d _ 8 p g 7 p g 6 k p f 7 pf 6 p f 5 vd d_ 4 v s s vs s v s s vs s v s s ph 1 2 pg 5 p g 4 pg 3 l p f1 0 p f9 p f8 regoff ph 1 1 p h 1 0 pd1 5 pg 2 m v s s a p c 0 p c 1 p c2 p c 3 pb 2 p g 1 vss _6 vss _7 v c ap 1 p h6 p h 8 p h9 p d 14 p d 13 nv r e f - p a 1 pa0- wk u p pa4 p c 4 pf 1 3 pg 0 v d d _ 6 vdd_7 v d d _ 1 pe 1 3 ph 7 p d 1 2 p d 1 1 p d 1 0 p v r e f + p a 2 p a 6 p a 5 p c5 p f 12 p f 15 pe 8 pe 9 p e 1 1 p e 1 4 pb 12 p b 13 p d 9 p d 8 r v dd a p a 3 p a 7 p b 1 p b 0 p f11 p f14 pe 7 p e 10 p e 1 2 p e 1 5 pb 10 p b 11 p b 14 p b 15 a i b vss 4 35 678 pinout s an d p i n d esc ription stm32f205xx, stm32f207xx 38/147 doc id 15818 rev 5 t a b l e 5. stm 32f 20x p i n a nd bal l d e f i ni t i o n s pins pi n name ty p e (1) i / o l e vel (2 ) main function (3 ) ( a ft er reset) alternate functions oth e r functions lq fp6 4 wlcsp64+ 2 lq fp100 lq fp144 lq fp176 ufb g a1 76 - - 1 1 1 a 2 pe2 i/o ft pe2 tr a ceclk/ fsmc_a2 3 / eth_mii_txd3 - - 2 2 2 a 1 pe3 i/o ft pe3 tra c ed 0/fsmc_a19 - - 3 3 3 b 1 pe4 i/o ft pe4 tra c ed1/ fsmc_ a 2 0 / dcmi_ d4 - - 4 4 4 b 2 pe5 i/o ft pe5 tra c ed2 / fsmc_a21 / tim9_ ch1 / dc mi_d6 - - 5 5 5 b 3 pe6 i/o ft pe6 tra c ed3 / fsmc_a22 / tim9_ ch2 / dc mi_d7 1a 9 6 6 6 c 1 v ba t sv ba t -- - - 7 d 2 p i 8 (4 ) i/o ft pi8 (5 ) rt c _ a f 2 2b 8 7 7 8 d 1 p c 1 3 (4 ) i/o ft pc13 (5 ) rt c _ a f 1 3 b 9 8 8 9 e1 pc14 (4 ) -osc3 2_in (6) i/o ft pc14 (5 ) osc32_in 4c 9 9 91 0 f 1 pc15 (4 ) - osc32_ out (6 ) i/o ft pc15 (5 ) osc32_ out - - - - 11 d3 pi9 i/o ft pi9 c an1_rx - - - - 12 e3 pi10 i/o ft pi10 eth_m ii_rx_er - - - - 13 e4 pi11 i/o ft pi11 o t g_ hs_ulpi_dir -- - - 1 4 f 2 v ss_ 13 sv ss _13 -- - - 1 5 f 3 v dd _1 3 sv dd _1 3 - - - 1 0 1 6 e2 pf0 i/o ft pf0 f smc_a0 / i2c2_sd a - - - 1 1 1 7 h 3 p f1 i/o ft pf1 f s mc_a1 / i2c2_s cl - - - 1 2 1 8 h 2 p f2 i/o f t pf2 f smc_a2 / i2c2_smba -- - 1 3 1 9 j2 p f 3 (6 ) i/o ft pf3 f s m c_a3 adc3_in9 -- - 1 4 2 0 j3 p f 4 (6 ) i/o ft pf4 f s m c_a4 adc3_in14 -- - 1 5 2 1 k 3 p f 5 (6 ) i/o ft pf5 f s m c_a5 adc3_in15 -h 9 1 0 1 6 2 2 g 2 v ss_5 sv ss_ 5 - - 1 1 17 23 g3 v dd _5 sv dd _5 -- - 1 8 2 4 k 2 p f 6 (6 ) i/o ft pf6 tim10 _ ch1 / fsmc_nio rd adc3_in4 -- - 1 9 2 5 k 1 p f 7 (6 ) i/o ft pf7 t im11_ ch1/fsmc_n r eg adc3_in5 -- - 2 0 2 6 l 3 p f 8 (6 ) i/o ft pf8 tim13 _ ch1 / fsmc_ n io w r adc3_in6 -- - 2 1 2 7 l 2 p f 9 (6 ) i/o ft pf9 t im1 4_ch1 / fsmc_cd a dc3_in7 stm 32f2 0 5 xx, stm32 f 20 7x x pinouts and pin description doc id 15818 rev 5 39/147 -- - 2 2 2 8 l 1 p f 1 0 (6 ) i/o ft pf10 fsmc_ i ntr a dc3_in8 5e 9 1 2 2 3 2 9 g 1 p h 0 (6) -o sc_i n i/o ft ph0 o sc_in 6f 9 1 3 2 4 3 0 h 1 p h 1 (6) - o sc_out i/o ft ph1 o sc_out 7 e8 1 4 2 5 3 1 j1 nrst i/o nrst 8g 9 1 5 2 6 3 2 m 2 p c 0 (6) i/o ft pc0 o tg_hs_ulpi_s tp adc12 3 _ in10 9f 8 1 6 2 7 3 3 m 3 p c 1 (6) i/o ft pc1 e th_mdc adc12 3 _ in11 10 d7 1 7 28 34 m4 pc2 (6) i/o ft pc2 spi2_miso / o t g_hs_ul p i_ dir / eth_mii_txd2 adc12 3 _ in12 11 g8 1 8 29 35 m5 pc3 (6) i/o ft pc3 spi2_mos i / i2s2_sd / o t g_hs_ulpi_nxt / eth_mii_tx_clk adc12 3 _ in13 - - 1 9 30 36 - v dd _1 2 sv dd _1 2 12 - 2 0 31 37 m 1 v ssa sv ss a -- - - - n 1 v ref- sv ref- -f 7 2 1 3 2 3 8 p 1 v ref+ sv ref+ 13 - 2 2 33 39 r 1 v dd a sv dd a 14 e7 2 3 34 40 n3 p a 0 (7 ) -wkup (6) i/o ft pa 0 - w k u p usar t2_c ts/ u a r t 4_tx/ eth_mii_crs / ti m2_ch1_e tr/ tim5_c h1 / tim8_etr adc1 23_c h0 /w kup 15 h8 2 4 35 41 n2 p a 1 (6) i/o ft pa 1 u s ar t2_r ts / ua r t 4 _ r x / eth_r m ii_ref_ clk / eth_mii_ rx_clk / tim5_c h2 / tim2_c h2 adc 123_ in1 16 j9 2 5 36 42 p2 p a 2 (6) i/o ft pa 2 us ar t2_tx/tim5_ch3 / tim9_ ch1 / tim2 _ch3 / eth_mdio adc 123_ in2 - - - - 43 f4 ph2 i/o ft ph2 e th_mii_c rs - - - - 44 g 4 ph3 i/o ft ph3 e th_mii_col - - - - 45 h4 ph4 i/o ft ph4 i2c2_scl / ot g _ h s _ u l p i _ n x t - - - - 46 j4 ph5 i/o ft ph5 i 2 c 2_sd a t a b l e 5. stm 32f 20x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pins pi n name ty p e (1 ) i / o le vel (2) main function (3 ) ( a ft er reset) alternate functions oth e r functions lq fp64 wlcsp64+2 lq fp10 0 lq fp14 4 lq fp17 6 ufbga 176 pinout s an d p i n d esc ription stm32f205xx, stm32f207xx 40/147 doc id 15818 rev 5 17 g7 2 6 37 47 r2 p a 3 (6) i/o ft pa 3 usar t2_rx/tim 5 _ch4 / tim9_ ch2 / tim2 _ch4 / o t g_hs_ulpi_d0 / eth_mii_col adc 123_ in3 18 f1 2 7 38 48 - v ss_4 sv ss_ 4 h7 l 4 regoff i/o regoff 19 e1 2 8 39 49 k4 v dd _4 sv dd _4 20 j8 2 9 40 50 n4 p a 4 (6) i/o p a 4 spi1_ns s / spi3_nss / usar t2_ck / dcmi_ hsync / o t g _ hs_sof / i2s3_w s adc12 _ in4 /d a c 1_out 21 h6 3 0 41 51 p4 p a 5 (6) i/o p a 5 sp i1_sck/ o t g_hs_ulpi_ck / / ti m2_ch1_e tr/ tim8_ chin adc12 _ in5 /d a c 2_out 22 h5 3 1 42 52 p3 p a 6 (6) i/o ft pa 6 spi1_miso / tim8_ bkin/tim13 _ ch1 / dcmi_ pixclk / tim3_ch 1 / t i m1_ b ki n adc12 _ in6 23 j7 3 2 43 53 r3 p a 7 (6) i/o ft pa 7 s p i1_m osi/ ti m8_ch1n / tim14_ ch1 tim3_ch2 / eth_mii_rx_d v / tim1_ch 1 n / rmii_ crs_d v adc12 _ in7 24 h4 3 3 44 54 n5 pc4 (6) i/o ft pc4 eth_rmii_ r x_d0 / eth_mii_rx_d0 adc 12_in14 25 g3 3 4 45 55 p5 pc5 (6) i/o ft pc5 eth_rmii_ r x_d1 / eth_mii_rx_d1 adc 12_in15 26 j6 3 5 46 56 r5 pb0 (6) i/o ft pb0 tim3_ ch3 / tim8_ ch2n/ o t g_hs_u lpi_ d1/ eth _ mii_rxd2 / tim1 _ch2n adc12 _ in8 27 j5 3 6 47 57 r4 pb1 (6) i/o f t pb1 tim3_ ch4 / tim8_ ch3n/ o t g_hs_u lpi_ d2/ eth _ mii_rxd3 / o t g _ hs _i nt n / tim1 _ch3n adc12 _ in9 28 j4 3 7 48 58 m6 pb2 i/o ft pb2- boo t 1 - - - 4 9 5 9 r 6 p f11 i/o ft pf11 dcmi_12 -- - 5 0 6 0 p 6 pf12 i/o f t p f 12 fs mc_a6 t a b l e 5. stm 32f 20x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pins pi n name ty p e (1 ) i / o le vel (2) main function (3 ) ( a ft er reset) alternate functions oth e r functions lq fp64 wlcsp64+2 lq fp10 0 lq fp14 4 lq fp17 6 ufbga 176 stm 32f2 0 5 xx, stm32 f 20 7x x pinouts and pin description doc id 15818 rev 5 41/147 -- - 5 1 6 1 m 8 v ss_6 sv ss_ 6 -- - 5 2 6 2 n 8 v dd _6 sv dd _6 - - - 5 3 6 3 n 6 p f1 3 i / o ft pf 13 f s mc_ a 7 - - - 5 4 6 4 r 7 p f1 4 i / o ft pf 14 f s mc_ a 8 - - - 5 5 6 5 p 7 p f15 i / o ft pf 15 f s mc_ a 9 - - - 5 6 6 6 n 7 p g0 i/o ft pg0 f smc_a10 - - - 5 7 6 7 m 7 p g1 i/o ft pg1 f smc_a11 - - 3 8 58 68 r8 pe7 i/o ft pe7 fsmc_ d 4/tim1_etr - - 3 9 59 69 p8 pe8 i/o ft pe8 fsmc_ d 5/tim1_ch 1 n - - 4 0 60 70 p9 pe9 i/o ft pe9 fsmc_ d 6/tim1_ch 1 -- - 6 1 7 1 m 9 v ss_7 sv ss_ 7 -- - 6 2 7 2 n 9 v dd _7 sv dd _7 - - 41 63 73 r9 p e 10 i/o f t pe10 f smc_d7/t im1_ch2n - - 42 64 74 p10 p e11 i/o ft pe11 f s m c_d8/tim1_ch2 - - 43 65 75 r10 p e12 i/o ft pe12 f smc_d9/tim1_ch3n - - 4 4 66 76 n1 1 p e1 3 i/o ft pe13 f smc_d10 / tim1 _ch3 - - 45 67 77 p11 p e14 i/o ft pe14 f smc_d11/tim 1 _ch4 - - 46 68 78 r11 p e15 i/o ft pe15 f smc_d12/tim 1 _bkin 29 h3 4 7 69 79 r1 2 p b1 0 i/o ft pb10 spi2_sck/ i2s2_ck/ i2c2 _scl / usar t3 _tx / o t g_hs_ulpi_d3 / et h_ mi i_ r x _e r / o t g_ hs_scl / tim2_ ch3 30 j2 4 8 70 80 r1 3 p b1 1 i/o ft pb11 i2c2_ s d a /u sar t 3_rx/ o t g_hs_ulpi_d4 / eth_rmii_tx_en/ eth_mii_ tx_en / o t g_hs_ s d a / tim2 _ch4 31 j3 4 9 71 81 m10 v cap_1 sv cap_1 32 - 5 0 72 82 n 1 0 v dd _1 sv dd _1 - - - - 83 m11 p h6 i/o ft ph6 i2c 2_smba / tim1 2_ch1 / eth_mii_rxd2 - - - - 84 n12 p h7 i/o ft ph7 i2c3_scl / eth_mii_rxd3 - - - - 85 m12 p h8 i/o ft ph8 i 2c3_sd a / dcmi_hsync t a b l e 5. stm 32f 20x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pins pi n name ty p e (1 ) i / o le vel (2) main function (3 ) ( a ft er reset) alternate functions oth e r functions lq fp64 wlcsp64+2 lq fp10 0 lq fp14 4 lq fp17 6 ufbga 176 pinout s an d p i n d esc ription stm32f205xx, stm32f207xx 42/147 doc id 15818 rev 5 - - - - 86 m13 p h9 i/o ft ph9 i2c3_smba / t i m 1 2_ch2/ dcmi_ d0 - - - - 87 l13 ph10 i/o ft ph10 tim5 _ch1_ e tr / dcmi_ d1 - - - - 88 l12 ph11 i/o ft ph1 1 tim5_ ch2 / dc mi_d2 - - - - 89 k1 2 p h1 2 i/o ft ph1 2 tim5_ ch3 / dc mi_d3 -- - - 9 0 h 1 2 v ss_ 14 sv ss _14 -- - - 9 1 j1 2 v dd _1 4 sv dd _1 4 33 j1 51 73 92 p12 p b12 i/o ft pb12 spi2_nss /i2s2_ws/ i2c 2_smba/ usar t3_ck/ tim1_bkin / ca n2 _ r x / o t g_hs_u lpi_ d5/ eth_rmii_ t xd0 / eth_mii_txd0/ ot g _ h s _ i d 34 h2 52 74 93 p13 p b13 i/o ft pb13 sp i2_sck / i2s2_ck / usar t3_ c ts/ tim1_c h1n /c an2_tx / o t g_hs_ulpi_d6 / eth_rmii_ t xd1 / eth_mii_txd1 ot g _ h s _ vb us 35 h1 5 3 75 94 r1 4 p b1 4 i/o ft pb14 s p i2_m iso/ ti m1_ch2n / tim12_ ch1 / o t g_hs_dm usar t3 _r ts/ tim8 _ch2n 36 g1 5 4 76 95 r1 5 p b1 5 i/o ft pb15 spi2_mos i / i2s2_sd / tim1_ch 3 n / tim8_c h3n / tim12_ ch2 / ot g _ h s _ d p - - 55 77 96 p15 p d8 i/o ft pd8 f sm c_d13 / usar t3_tx - - 56 78 97 p14 p d9 i/o ft pd9 f smc_d14 / usar t3_rx - - 5 7 79 98 n1 5 p d1 0 i/o ft pd1 0 fsmc_ d 15 / usar t3 _ck - - 58 8 0 9 9 n 1 4 p d 1 1 i/o f t pd11 f s mc_a 16 /usar t3 _ c t s - - 59 8 1 1 0 0 n 13 pd 12 i/o f t pd 12 f s mc_a 17/t im4_ch1 / usar t3_r ts - - 6 0 82 10 1 m 15 pd1 3 i/o ft pd1 3 fsmc_a18 /tim4 _ ch2 -- - 8 3 1 0 2 - v ss_8 sv ss_ 8 -- - 8 4 1 0 3 j1 3 v dd _8 sv dd _8 t a b l e 5. stm 32f 20x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pins pi n name ty p e (1 ) i / o le vel (2) main function (3 ) ( a ft er reset) alternate functions oth e r functions lq fp64 wlcsp64+2 lq fp10 0 lq fp14 4 lq fp17 6 ufbga 176 stm 32f2 0 5 xx, stm32 f 20 7x x pinouts and pin description doc id 15818 rev 5 43/147 - - 6 1 85 10 4 m 14 pd1 4 i/o ft pd1 4 fsmc_ d 0/tim4_ch 3 - - 6 2 86 10 5 l14 pd1 5 i/o ft pd1 5 fsmc_ d 1/tim4_ch 4 - - - 8 7 1 06 l15 pg2 i/o ft pg2 f smc_a12 - - - 8 8 1 07 k15 p g3 i/o ft pg3 f smc_a13 - - - 8 9 1 08 k14 p g4 i/o ft pg4 f smc_a14 - - - 9 0 1 09 k13 p g5 i/o ft pg5 f smc_a15 - - - 9 1 1 10 j15 p g6 i/o f t pg 6 f smc_int 2 - - - 9 2 1 11 j14 p g7 i/o f t pg 7 f smc_int3 / u sar t6_ck - - - 9 3 1 12 h14 p g 8 i/o f t pg 8 u s ar t6_r ts / eth_pps_out -- - 9 4 1 1 3 g 1 2 v ss_9 sv ss_ 9 -- - 9 5 1 1 4 h 1 3 v dd _9 sv dd _9 37 g2 6 3 96 11 5 h 1 5 pc6 i/o ft pc6 spi2_mck / tim8 _ch1 /sdio_ d6 / usar t6_tx / dcmi_d0/tim3_c h1 38 f2 6 4 97 11 6 g 15 pc 7 i/o ft pc7 spi3_mck / tim8 _ch2 /sdio_ d7 / usar t6_rx / dcmi_d1/tim3_c h2 39 f3 6 5 98 11 7 g 14 pc 8 i/o ft pc8 tim8_ ch3/sdio_d 0 /ti m3_ch3/ usa r t6_ck / dcmi_ d2 40 d1 6 6 99 11 8 f 14 pc9 i/o ft pc9 i2s2_ckin/ i2s3_ckin/ mco2 / tim8 _ch4 /sdio_ d1 / /i 2c3_sd a / dcm i _d3 / tim3 _ch4 41 e2 6 7 100 11 9 f 15 p a 8 i/o ft p a 8 mco1 / usar t1_ck/ t i m1 _ch1 / i2 c3_sc l / ot g _ f s _ s o f 42 e3 6 8 101 12 0 e 1 5 p a 9 i/o ft p a 9 usar t1_tx/ tim1_ch2 / i2c3_smb a / dcm i _d0 ot g _ f s _ vb us 43 d3 6 9 102 12 1 d 1 5 p a 1 0 i/o ft p a 10 usar t1_rx/ tim1_ch3/ o t g_ fs_id/dcmi_ d1 44 d2 7 0 103 12 2 c 1 5 p a 1 1 i/o ft p a 11 usar t1_c ts / can1_ r x / ti m1_ch4 / o t g_fs_dm t a b l e 5. stm 32f 20x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pins pi n name ty p e (1 ) i / o le vel (2) main function (3 ) ( a ft er reset) alternate functions oth e r functions lq fp64 wlcsp64+2 lq fp10 0 lq fp14 4 lq fp17 6 ufbga 176 pinouts and pin description stm32f205xx, stm32f207xx 44/147 doc id 15818 rev 5 45 c1 71 104 123 b15 pa12 i/o ft pa12 usar t1_r ts / can1_ t x/ t i m1 _etr / o t g_ fs_d p 46 b2 7 2 105 12 4 a 1 5 p a 1 3 i/o ft jtms- swdio jtm s -swdio 47 c2 7 3 106 12 5 f 13 v cap_2 sv cap_2 - b 1 7 4 107 12 6 f 12 v ss_2 sv ss_ 2 48 a8 7 5 108 12 7 g 13 v dd _2 sv dd _2 - - - - 12 8 e 1 2 ph13 i/o ft ph1 3 tim8_ch 1 n / can1_ t x - - - - 12 9 e 1 3 ph14 i/o ft ph1 4 tim8_ ch2n / dc mi_d 4 - - - - 13 0 d 1 3 ph1 5 i/o ft ph1 5 tim8 _ch3 n / dcmi_ d11 - - - - 131 e 14 pi0 i/o ft pi0 ti m5_ch4 / spi2_ns s / i2s2_ w s / dcmi_d13 - - - - 132 d 14 pi1 i/o ft pi1 sp i2_sck / i2s2_ck / dcmi_ d8 - - - - 133 c 14 pi2 i/o ft pi2 tim8_ch4 /spi2_miso / dcmi_ d9 - - - - 134 c 13 pi3 i/o ft pi3 tim8_etr / spi2_mosi / i2s2_sd / dc mi_d1 0 -- - - 1 3 5 d 9 v ss_ 15 sv ss _15 -- - - 1 3 6 c 9 v dd _1 5 sv dd _1 5 49 a1 7 6 109 13 7 a 1 4 p a 1 4 i/o ft jtck- swclk jtck -swclk 50 a2 7 7 110 13 8 a 1 3 i/o ft jtdi jt di/ spi3_ns s / i 2 s3_ws/ ti m2_ch1_e tr / spi1_nss 51 b3 7 8 111 13 9 b 1 4 pc10 i/o ft pc1 0 sp i3_sck / i2s3_ck / u a r t 4_tx / sdio_d2 / dcmi_ d8 / usar t3 _tx 5 2 c 3 79 1 1 2 1 4 0 b 13 pc 11 i/o f t pc 11 u a r t 4_rx/ spi3_miso / sdio_d3 / dcmi_d4/usar t3 _rx 5 3 a3 80 1 1 3 1 4 1 a 12 pc12 i/o f t pc12 u a r t 5_tx/sdio_ck / dcmi_d9 / s p i3_m osi / i2s3_sd / usar t3_ck - - 8 1 114 14 2 b 1 2 pd0 i/o ft pd0 f smc_d2 /c an 1_rx - - 8 2 115 14 3 c 1 2 pd 1 i/o ft pd1 f smc_d3 / c a n 1_tx t a b l e 5. stm 32f 20x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pins pi n name ty p e (1 ) i / o le vel (2) main function (3 ) ( a ft er reset) alternate functions oth e r functions lq fp64 wlcsp64+2 lq fp10 0 lq fp14 4 lq fp17 6 ufbga 176 stm32f205xx, stm32f207xx pinouts and pin description doc id 15818 rev 5 45/147 54 c7 8 3 116 14 4 d 1 2 pd2 i/o ft pd2 tim3_etr/u ar t5_rx sdio_cmd / dcmi_d11 - - 84 117 145 d 11 pd3 i/o ft pd3 f smc_clk / usar t2_cts - - 85 118 146 d 10 pd4 i/o ft pd4 f sm c_noe/usar t2_r ts - - 86 119 147 c 11 pd5 i/o ft pd5 f smc_nwe/usar t2_tx - - - 120 14 8 d 8 v ss_ 10 sv ss _10 - - - 121 14 9 c 8 v dd _1 0 sv dd _1 0 - - 8 7 122 15 0 b 1 1 pd 6 i/o ft pd6 fsmc_nw a it/usar t2_r x - - 8 8 123 15 1 a 1 1 pd7 i/o ft pd7 usar t2_ck / fsm c _ne1/f smc_ nce2 - - - 124 15 2 c 1 0 pg9 i/o ft pg9 usar t6_rx / fsmc_ne2/fsm c_nce3 - - - 125 15 3 b 1 0 pg10 i/o ft pg1 0 fsmc_n ce4_1 / fsmc_ n e3 - - - 126 15 4 b 9 p g11 i/o ft pg1 1 fsmc_ nce4_2 / eth_mii_tx_en - - - 127 15 5 b 8 p g12 i/o ft pg1 2 fsmc_ne4 / usar t6_r ts - - - 128 15 6 a 8 p g13 i/o ft pg1 3 fsmc_a2 4 / usar t6_cts /eth_mii_ t xd0/eth_rmii _t xd 0 - - - 129 15 7 a 7 p g14 i/o ft pg1 4 fsmc_a25 / u s ar t6_tx /eth_mii_ t xd1/eth_rmii _t xd 1 - - - 130 15 8 d 7 v ss_ 11 sv ss _11 - - - 131 15 9 c 7 v dd _1 1 sv dd _1 1 - - - 132 160 b 7 p g15 i/o f t pg 15 usar t 6 _ct s / dcm i _d13 55 a4 8 9 133 16 1 a 1 0 pb3 i/o ft jtdo/ tra c esw o jtdo/ tra c esw o/ sp i3_sck / i2s3_ck / tim2_ch2 / spi1_sck 56 b4 9 0 134 16 2 a 9 pb4 i/o ft n j trst njtrst/ spi3_mis o / tim 3 _ch1 / s p i1_m iso t a b l e 5. stm 32f 20x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pins pi n name ty p e (1 ) i / o le vel (2) main function (3 ) ( a ft er reset) alternate functions oth e r functions lq fp64 wlcsp64+2 lq fp10 0 lq fp14 4 lq fp17 6 ufbga 176 pinout s an d p i n d esc ription stm32f205xx, stm32f207xx 46/147 doc id 15818 rev 5 57 a5 91 135 163 a6 pb5 i/o ft pb5 i2 c1_smba/ can2 _rx / o t g_hs_ulpi_d7 / e t h_pps_out/tim3_ch2 / spi1_mosi/ spi3_mosi / dcmi_d10 / i2s3 _sd 58 b5 92 136 164 b6 pb6 i/o ft pb6 i2 c1_scl / tim4_c h1 / can2_tx /o tg_fs_intn / dcmi_d5/usar t1 _tx 59 a6 93 137 165 b5 pb7 i/o ft pb7 i2 c1_sd a / fsmc_nl (8) / dcmi_vsync / usar t1_rx/ tim4_ch2 60 b6 9 4 138 16 6 d 6 b oo t0 i b oo t0 v pp 61 b7 95 139 167 a5 pb8 i/o ft pb8 tim4 _ch3/sdio_ d4/ tim10_ ch1 / dc mi_d6 / o t g_ fs_scl / eth_mii_txd3 / i2c1_s c l / can1 _rx 62 a7 96 140 168 b4 pb9 i/o ft pb9 sp i2_nss/ i2s2_ws / tim4_ ch4/ tim11_c h1/ o t g_fs_sd a / sdio_d5 / dcmi_d7 / i2c1_sd a / can 1_tx - - 97 141 169 a 4 pe0 i/o ft pe0 ti m4_et r / fsm c _nbl0 / dcmi_ d2 - - 9 8 142 17 0 a 3 pe1 i/o ft pe1 fsmc_ n bl1 / d c mi_d 3 -d 5 v ss sv ss 63 d8 - - - - v ss_ 3 sv ss_ 3 - - 9 9 143 17 1 c 6 r fu (9) 64 d9 100 144 17 2 c 5 v dd _3 sv dd _3 - - - - 173 d 4 p i4 i/o ft pi4 t im8_bkin / dcm i _d5 - - - - 174 c 4 p i5 i/o ft pi5 t im8_ch1 / dcmi_vsync - - - - 175 c 3 p i6 i/o ft pi6 t im8_ ch2 / dc mi_d6 - - - - 176 c 2 p i7 i/o ft pi7 t im8_ ch3 / dc mi_d7 - c 8 - - - - i rr of f i/o irr o f f 1. i = input, o = output, s = supply, hiz = h i gh impedance. 2. ft = 5 v tolerant. 3. fu nction availability depends on the chosen de vice. t a b l e 5. stm 32f 20x p i n a nd bal l d e f i ni t i o n s (c ont in u e d) pins pi n name ty p e (1 ) i / o le vel (2) main function (3 ) ( a ft er reset) alternate functions oth e r functions lq fp64 wlcsp64+2 lq fp10 0 lq fp14 4 lq fp17 6 ufbga 176 stm32f205xx, stm32f207xx pinouts and pin description doc id 15818 rev 5 47/147 4. pc13, pc 14, pc15 and p i8 are supplied through the power sw itch. since th e sw itch only sinks a limited amou nt of curren t (3 ma ), the use of gpios pc13 to pc15 and p i 8 in ou tput mode is limited: the sp eed should not exceed 2 mhz with a maximu m load o f 30 pf a nd these i/os must not b e us ed as a current source (e.g. to drive an led). 5. main functio n after th e first ba ckup domain pow er-up . later o n, it de pends on the contents of the r t c registers even afte r re set (because these registers are not rese t by the main reset). f o r det ails o n how to man age these i/os, refer t o the rt c re gister d escription se ctions in th e stm32f 20x and stm32f 21x reference manual, ava i lable fr om the st microe lectron i cs website: www .st.com. 6. ft = 5 v tolerant e x cept when in an alog mo de or oscilla t or mode (for pc 1 4, pc15, ph0 a nd ph1). 7. if the device is delivere d in an ufbga176 package and if the regoff pin is set to v dd (regulator in bypass mode), the n pa0 is used as an intern al re set (active low). 8. fsmc _nl pin is also named f s mc _nadv on memory d evices. 9. rf u = reserved for futur e use . pinouts and pin description stm32f205xx, stm32f207xx 48/147 doc id 15818 rev 5 t a b l e 6. alte rna t e f unc tion mapp in g po r t af0 a f 1 af 2 a f3 af4 a f 5 af6 a f7 af8 a f 9 af10 af11 af12 af13 af014 af15 sy s t i m1/2 t im3/ 4/5 t im8/ 9/10/ 1 1 i2c 1 /i2c2/i 2c3 s pi1 / sp i2/i2s 2 sp i3/i2s 3 usar t1/2/3 ua r t 4 / 5 / us ar t6 can1/can2/ t i m12/1 3 /14 ot g _ f s / ot g _ h s e t h fsm c /sdio / ot g _ f s dc m i pa 0 - w k u p t i m2_c h1 ti m2 _ e tr ti m 5_c h1 ti m8_etr usar t 2 _cts u a r t 4_ t x eth_mi i _ cr s event o ut p a 1 t im2_c h2 t i m5_c h2 usar t 2_r ts u a r t 4_rx et h_ mi i _r x_clk eth _ rmii _ref _clk event o ut p a 2 t i m 2_c h3 ti m5_c h3 ti m9_ch 1 usar t 2_tx et h _ mdi o event o ut p a 3 t i m 2_c h4 ti m5_c h4 ti m9_ch 2 usar t2_rx o t g _ hs_ulpi _ d0 e t h _ m i i _c o l event o ut pa 4 spi 1_nss spi 3_ nss i2 s3_w s usar t2_ck o t g _ hs_sof d c mi _h sy n c event o ut pa 5 t i m2_c h1 ti m2 _ e tr ti m8_ ch1n spi 1_sck o t g_hs_ u lpi _ c k event o ut p a 6 t i m 1_bkin t i m3_c h1 t i m8_bkin s p i 1_miso t i m13_c h1 dc mi_pixck event o ut p a 7 t im1_ ch1n t i m3_c h2 t i m8_ ch1n s p i 1_mo s i t i m14_c h1 et h _ m i i _ r x _ d v et h_rmi i _c rs_d v event o ut p a 8 m co 1 t im1_c h1 i2c3_ s c l usar t 1_ck o t g_f s _so f event o ut p a 9 t im1_c h2 i 2 c3_smba u sar t1_t x dcmi _ d 0 event o ut p a 10 t i m1_c h3 usar t1_rx o t g_fs_i d dcmi _ d 1 event o ut p a 11 t i m1_c h4 usar t1 _ct s can 1_rx o t g _f s_dm event o ut p a 12 t i m1_et r usar t 1_r ts c a n1_t x o tg _fs_ dp event o ut pa 1 3 j t m s - s w d i o event o ut p a 14 j t ck- s w c lk event o ut pa 1 5 j t d i t i m 2_c h1 ti m 2 _ e tr spi 1_nss spi 3_ nss i2 s3_w s event o ut pb0 tim1_ ch2n t i m3_c h3 t i m8_ ch2n o t g _ hs_ulpi _ d1 eth _mi i _rxd2 event o ut pb1 tim1_ ch3n t i m3_c h4 t i m8_ ch3n o t g _ hs_ulpi _ d2 eth _mi i _rxd3 o t g _ hs_i ntn event o ut pb2 event o ut pb3 jtd o / tra c e sw o t i m2_c h2 spi 1_sck spi 3_ s c k i 2 s3_ c k event o ut pb4 j t rst ti m3_c h1 s pi 1_mi so spi 3 _ mi so event o ut pb5 t i m3_c h2 i 2 c1_smba s pi 1_mo s i spi 3 _ mo si i2s 3 _ s d can 2_rx o t g _ hs_ulpi _ d7 eth _pps_out d c mi _d 10 event o ut pb6 ti m4_c h1 i 2 c1_ s c l usar t 1_tx c a n2_tx o t g _ fs_i ntn dcmi _ d 5 event o ut pb7 t i m4_c h2 i2c1 _sd a usar t 1_rx f s mc _nl dcmi _ v syn c event o ut pb8 t i m4_c h3 t i m10_c h1 i2c1_ s c l can 1_rx o t g_f s _sc l et h _mi i _txd3 sdi o _d 4 dcmi _ d 6 event o ut pb9 t i m4_c h4 t i m11_c h1 i2c1 _sd a spi 2_nss i 2 s2_w s c a n1_tx o t g_fs _ s d a sdi o _d 5 dcmi _ d 7 event o ut p b 1 0 t im 2_c h3 i2c2_ s c l spi 2_sck i 2 s2_ck usar t 3_tx o t g _ hs_ulpi _ d3 et h_ mi i _ rx_er o t g _hs_sc l event o ut pb11 t im2_c h4 i2c2 _sd a usar t 3_rx o t g_ hs_ulpi _ d4 et h _mi i _tx_ e n e t h _ r m ii_ tx _e n o t g_h s _ s d a event o ut pb12 t i m 1_bki n i 2 c2_smba spi 2_nss i 2 s2_w s usar t 3_ck can 2_rx o t g_ hs_ulpi _ d5 eth _mii_t xd0 e t h _ r m i i _ tx d0 o t g _ h s _i d event o ut pb13 t i m 1_ ch1n spi 2_sck i 2 s2_ck usar t3 _ct s c a n2_t x o t g_ hs_ulpi _ d6 eth _mii_t xd1 e t h _ r m i i _ tx d1 event o ut pb14 t im1_ ch2n t i m8_ ch2n s p i 2_miso u sar t 3_r t s t i m12_c h1 o t g _ hs_dm event o ut stm32f205xx, stm32f207xx pinouts and pin description doc id 15818 rev 5 49/147 pb15 r t c _50h z tim1_ ch3n t i m8_ ch3n s p i 2_mo s i i2 s 2 _ s d t i m12_c h2 o t g _ hs_d p event o ut pc0 o t g_hs_u lpi _ stp event o ut pc1 eth_mdc event o ut pc2 s p i 2_mi s o o t g _hs_ul pi _di r et h _mi i _txd2 event o ut pc3 s p i 2_mo s i o tg _hs_u l pi_nxt et h _mii _tx_c l k e t h _r m i i _t x _ c lk event o ut pc4 et h_mii _ rxd0 eth_ rmii_ r xd0 event o ut pc5 et h _mi i _rxd1 eth _rmii _ rxd1 event o ut pc6 t i m 3_c h1 ti m8_ch 1 i 2 s2_mck usar t 6 _ t x sdi o _d 6 dcmi _ d 0 event o ut pc7 t i m 3_c h2 ti m8_ch 2 i 2 s3_sck u s a r t6_rx sdi o _d 7 dcmi _ d 1 event o ut pc8 t im3_c h3 t i m8_ch 3 u s a r t6_ck sdi o _d 0 dcmi _ d 2 event o ut pc9 m co 2 t im3_c h4 t i m8_ch 4 i2c3 _sd a i 2 s2_cki n i 2 s 3_ckin sdi o _d 1 dcmi _ d 3 event o ut pc10 spi 3_ s c k i 2 s3_ c k usar t 3_tx u a r t 4_ t x sdi o _d 2 dcmi _ d 8 event o ut pc11 spi 3 _ mi so usar t3_rx u a r t 4_rx sdi o _d 3 dcmi _ d 4 event o ut pc12 spi 3 _ mo si i2s 3 _ s d usar t3_ck u a r t 5_ t x sdi o _ck dcmi _ d 9 event o ut pc13 p c 14- osc3 2_in p c 15- osc 32_o ut pd0 can 1_rx f s mc _d2 event o ut pd1 c a n1_tx f s mc _d3 event o ut pd2 t im3_et r u a r t 5_rx s d i o _cmd d c mi _d 11 event o ut pd3 usar t 2 _cts fsmc_cl k event o ut pd4 usar t2_r t s f s mc_n o e event o ut pd5 usar t 2_tx fs mc _nwe event o ut pd6 usar t2_rx f s mc_ n w a i t event o ut pd7 usar t2_ck fsmc_ne1 event o ut pd8 usar t 3_tx f s mc_ d 13 event o ut pd9 usar t3_rx f s mc_ d 14 event o ut pd10 usar t3_ck f s mc_ d 15 event o ut pd11 usar t 3 _cts f s mc _a16 event o ut pd12 t i m4_c h1 usar t3_r t s f s mc _a17 event o ut pd13 t i m4_c h2 f s mc _a18 event o ut pd14 t i m4_c h3 f s mc _d0 event o ut t a b l e 6. alte rna t e f unc tion mapp in g ( c o n tin u ed ) po r t af0 a f 1 af 2 a f3 af4 a f 5 af6 a f7 af8 a f 9 af10 af11 af12 af13 af014 af 1 5 sy s t i m1/2 t im3/ 4/5 t im8/ 9/10/ 1 1 i2c 1 /i2c2/i 2c3 s pi1 / sp i2/i2s 2 sp i3/i2s 3 usar t1/2/3 ua r t 4 / 5 / us ar t6 can1/can2/ t i m12/1 3 /14 ot g _ f s / ot g _ h s e t h fsm c /sdio / ot g _ f s dc m i pinouts and pin description stm32f205xx, stm32f207xx 50/147 doc id 15818 rev 5 pd15 t i m4_c h4 f s mc _d1 event o ut pe0 ti m4 _ e tr fsmc_nbl0 dcmi _ d 2 event o ut pe1 fsmc_bln1 dcmi _ d 3 event o ut pe2 t r a c ec lk et h _mi i _txd3 f s mc _a23 event o ut pe3 tra c ed0 f s mc _a19 event o ut pe4 tra c ed1 f s mc _a20 dcmi _ d 4 event o ut pe5 tra c ed2 ti m9_ch 1 f s mc _a21 dcmi _ d 6 event o ut pe6 tra c ed3 ti m9_ch 2 f s mc _a22 dcmi _ d 7 event o ut pe7 ti m1 _ e tr f s mc _d4 event o ut pe8 t i m1_ ch1n f s mc _d5 event o ut pe9 ti m1_c h1 f s mc _d6 event o ut pe10 t i m 1_ ch2n f s mc _d7 event o ut pe11 t i m 1_c h2 f s mc _d8 event o ut pe12 t i m 1_ ch3n f s mc _d9 event o ut pe13 t i m 1_c h3 f s mc_ d 10 event o ut pe14 t i m 1_c h4 f s mc_ d 11 event o ut pe15 t i m 1_bki n f s mc_ d 12 event o ut pf0 i2c2 _s d a f s mc _a0 event o ut pf1 i2c2_ s c l f s mc _a1 event o ut pf2 i 2 c2_smba f s mc _a2 event o ut pf3 f s mc _a3 event o ut pf4 f s mc _a4 event o ut pf5 f s mc _a5 event o ut pf 6 t im10_c h1 f s mc_ n i o rd event o ut pf 7 t im11_c h1 f s mc _nreg event o ut pf8 t i m13_c h1 f s mc_nio w r event o ut pf9 t i m14_c h1 f s mc_cd event o ut pf10 f s mc _i ntr event o ut pf11 d c mi _d 12 event o ut pf12 f s mc _a6 event o ut pf13 f s mc _a7 event o ut pf14 f s mc _a8 event o ut pf15 fsmc_a9 eventout t a b l e 6. alte rna t e f unc tion mapp in g ( c o n tin u ed ) po r t af0 a f 1 af 2 a f3 af4 a f 5 af6 a f7 af8 a f 9 af10 af11 af12 af13 af014 af 1 5 sy s t i m1/2 t im3/ 4/5 t im8/ 9/10/ 1 1 i2c 1 /i2c2/i 2c3 s pi1 / sp i2/i2s 2 sp i3/i2s 3 usar t1/2/3 ua r t 4 / 5 / us ar t6 can1/can2/ t i m12/1 3 /14 ot g _ f s / ot g _ h s e t h fsm c /sdio / ot g _ f s dc m i stm32f205xx, stm32f207xx pinouts and pin description doc id 15818 rev 5 51/147 pg 0 f s mc _a10 event o ut pg 1 f s mc _a11 event o ut pg 2 f s mc _a12 event o ut pg 3 f s mc _a13 event o ut pg 4 f s mc _a14 event o ut pg 5 f s mc _a15 event o ut pg 6 fsmc_i nt 2 event o ut pg 7 u s a r t6_ck fsmc_i nt 3 event o ut pg 8 u s ar t6_r ts eth _pps_out event o ut pg 9 u s a r t6_rx fsmc_ne2 event o ut pg 1 0 f s mc_n ce4_1 event o ut pg 1 1 et h _mi i _tx_ e n e t h _ r m ii_ tx _e n f s mc_n ce4_2 event o ut pg 1 2 u s ar t6_r ts fsmc_ne4 event o ut pg 1 3 u a r t 6_ct s eth _mii_t xd0 e t h _ r m i i _ tx d0 f s mc _a24 event o ut pg 1 4 usar t 6 _ t x eth _mii_t xd1 e t h _ r m i i _ tx d1 f s mc _a25 event o ut pg 1 5 usar t6_cts d c mi _d 13 event o ut ph 0 - o s c _ i n p h 1 - osc _ ou t ph2 eth _mi i _cr s event o ut ph3 e t h _ m i i _c o l event o ut ph4 i2c2_ s c l o t g_hs_u lpi _ nxt event o ut ph5 i2c2 _s d a event o ut ph6 i 2 c2_smba t i m12_c h1 et h _mi i _rxd2 event o ut ph7 i2c3_ s c l eth _mi i _rxd3 event o ut ph8 i2c3 _s d a d c mi _h sy n c event o ut ph9 i 2 c3_smba t i m12_c h2 dcmi_d 0 event o ut ph10 t i m5_c h1t i m5_et r dcmi _ d 1 event o ut ph11 t i m5_c h2 dcmi _ d 2 event o ut ph12 t i m5_c h3 dcmi _ d 3 event o ut ph13 t i m8_ ch1n c a n1_t x event o ut ph14 t i m8_ ch2n dcmi _ d 4 event o ut ph15 t i m8_ ch3n d c mi _d 11 event o ut t a b l e 6. alte rna t e f unc tion mapp in g ( c o n tin u ed ) po r t af0 a f 1 af 2 a f3 af4 a f 5 af6 a f7 af8 a f 9 af10 af11 af12 af13 af014 af 1 5 sy s t i m1/2 t im3/ 4/5 t im8/ 9/10/ 1 1 i2c 1 /i2c2/i 2c3 s pi1 / sp i2/i2s 2 sp i3/i2s 3 usar t1/2/3 ua r t 4 / 5 / us ar t6 can1/can2/ t i m12/1 3 /14 ot g _ f s / ot g _ h s e t h fsm c /sdio / ot g _ f s dc m i pinouts and pin description stm32f205xx, stm32f207xx 52/147 doc id 15818 rev 5 pi0 tim5_ch4 spi 2_nss i 2 s2_w s d c mi _d 13 event o ut pi 1 spi 2_sck i 2 s2_ck dcmi _ d 8 event o ut pi 2 t im8_ch 4 s p i 2_miso dcmi _ d 9 event o ut pi 3 t im8_et r s p i 2_mo s i i2 s 2 _ s d d c mi _d 10 event o ut pi 4 t i m 8_bki n dcmi _ d 5 event o ut pi 5 t im8_ch 1 dcmi _ v syn c event o ut pi 6 t im8_ch 2 dcmi _ d 6 event o ut pi 7 t im8_ch 3 dcmi _ d 7 event o ut pi 8 pi 9 can 1_rx event o ut pi 1 0 et h _mi i _ rx_er event o ut pi 1 1 o t g_hs_ul p i _ di r event o ut t a b l e 6. alte rna t e f unc tion mapp in g ( c o n tin u ed ) po r t af0 a f 1 af 2 a f3 af4 a f 5 af6 a f7 af8 a f 9 af10 af11 af12 af13 af014 af 1 5 sy s t i m1/2 t im3/ 4/5 t im8/ 9/10/ 1 1 i2c 1 /i2c2/i 2c3 s pi1 / sp i2/i2s 2 sp i3/i2s 3 usar t1/2/3 ua r t 4 / 5 / us ar t6 can1/can2/ t i m12/1 3 /14 ot g _ f s / ot g _ h s e t h fsm c /sdio / ot g _ f s dc m i stm32f205xx, stm32f207xx memory mapping doc id 15818 rev 5 53/147 4 memor y mapping th e me mor y ma p is sho w n in fig u r e 15 . figu re 15 . m emor y map - b y t e b l o c k # o r t e x - g s i n t e r n a l p e r i p h e r a l s - b y t e b l o c k . o t u s e d - b y t e b l o c k & 3 - # r e g i s t e r s - b y t e b l o c k & 3 - # b a n k b a n k - b y t e b l o c k & 3 - # b a n k b a n k - b y t e b l o c k 0 e r i p h e r a l s - b y t e b l o c k 3 2 ! - x x & & & & & & & x x & & & & & & & x x & & & & & & & x x & & & & & & & x x & & & & & & & x ! x " & & & & & & & x # x $ & & & & & & & x % x & & & & & & & & - b y t e b l o c k # o d e & l a s h x x & & & & & & & x & & & x & & & ! & x & & & # x & & & # x x & & & & & x # x & & & & & & x x & & & & & 3 y s t e m m e m o r y 2 e s e r v e d 2 e s e r v e d ! l i a s e d t o & l a s h s y s t e m m e m o r y o r 3 2 ! - d e p e n d i n g o n t h e " / / 4 p i n s 3 2 ! - + " a l i a s e d b y b i t b a n d i n g 2 e s e r v e d x x " & & & x # x & & & & x x & & & & & & & 4 ) - 4 ) - x x & & 4 ) - 4 ) - 4 ) - 4 ) - 2 e s e r v e d x x & & x x " & & x # x & & & x x & & x x & & x x & & 2 4 # " + 0 r e g i s t e r s x x " & & 7 7 $ ' x # x & & & ) 7 $ ' x x & & 2 e s e r v e d x x & & 3 0 ) ) 3 x x " & & 3 0 ) ) 3 x # x & & & 2 e s e r v e d x x & & 5 3 ! 2 4 x x & & x x " & & 5 3 ! 2 4 5 ! 2 4 x # x & & & 5 ! 2 4 x x & & ) # x x & & ) # x x " & & 2 e s e r v e d x # x & & & x x & & 0 7 2 x x & & $ ! # $ ! # x x & & & & 4 ) - 0 7 - x x & & 4 ) - 0 7 - x x & & 0 o r t ! 5 3 ! 2 4 x x & & x x & & 0 o r t " x x & & & 0 o r t # x x & & 0 o r t $ x x & & 0 o r t % x x " & & 0 o r t & x # x & & & 0 o r t ' x x & & 2 e s e r v e d x x & & x x " & & x x & & x x & & 5 3 ! 2 4 x x " & & 2 e s e r v e d x x & & x # x & & & x x & & x x & & 2 e s e t c l o c k c o n t r o l l e r 2 # # x x " & & 0 o r t ( x # x & & & & l a s h i n t e r f a c e x x & & 2 e s e r v e d x x & & & # 2 # x x & & & 3 - # b a n k . / 2 0 3 2 ! - x x & & & & & & & 3 - # b a n k . / 2 0 3 2 ! - x x & & & & & & & 3 - # b a n k . / 2 0 3 2 ! - x x " & & & & & & & 3 - # b a n k . / 2 0 3 2 ! - x # x & & & & & & & & 3 - # b a n k . ! . $ . ! . $ x x & & & & & & & & 3 - # b a n k . ! . $ . ! . $ x x & & & & & & & & 3 - # b a n k 0 # # a r d x x & & & & & & & & 3 - # c o n t r o l r e g i s t e r x ! x ! & & & 2 e s e r v e d x ! x " & & & & & & & a i / p t i o n " y t e s 4 ) - 3 9 3 # & ' x x & & x x " & & 3 $ ) / 2 e s e r v e d 2 e s e r v e d x # x & & & & % 8 4 ) x # x & & & 2 e s e r v e d " x # ! . x x & & x x & & x x " & & x x & & & & & & & 2 e s e r v e d x x & & $ # - ) x x & & & 2 e s e r v e d x x & & & & 5 3 " / 4 ' & 3 x x & & & & & & & 2 e s e r v e d x x & & & & 5 3 " / 4 ' ( 3 2 e s e r v e d x x & & & & x x & & % 4 ( % 2 . % 4 2 e s e r v e d x x & & & x x & & x x & & $ - ! $ - ! 2 e s e r v e d x x & & & x x & & & " + 0 3 2 ! - x # x & & & x x " & & 2 e s e r v e d x x & & 0 o r t ) 4 ) - 4 ) - 3 0 ) ! $ # ! $ # ! $ # 2 e s e r v e d " x # ! . x # x & & & ) # 2 e s e r v e d 4 ) - 4 ) - 4 ) - x # x & & & x x " & & x x & & 3 2 ! - + " a l i a s e d b y b i t b a n d i n g 2 e s e r v e d x & & & # x & & & & & & & x & & & ! x & & & & & & 2 e s e r v e d 2 e s e r v e d x x & & & 2 . ' 2 e s e r v e d x x & & & electrical characteristics stm32f205xx, stm32f207xx 54/147 doc id 15818 rev 5 5 electrical c h aracteristics 5. 1 p a rameter conditions unle ss ot he rwise sp ecif ied, all v o lt ag es a r e r e f e r e n c e d to v ss . 5.1.1 minim u m and maxim u m v a lues unle ss ot he rwise sp ecif ied t h e min i m u m an d ma xim u m v a lue s ar e gu ar a n t eed in th e w o rst con d it ion s of a m bie n t t e mp er a t u r e , sup p ly v o lta ge an d f r equ encie s b y t e st s in pr od uctio n on 1 00% of th e de vices with a n amb i en t t e mp er a t u r e a t t a = 25 c a n d t a = t a ma x (g iv e n b y t h e sele cte d te mpe r at ur e r a nge ). dat a based on ch ar a c te r i za tio n r e sult s , de si gn sim u la t i on a n d / o r t e chn o lo gy char acte r i st ics a r e in dicat e d in t h e t a b l e f o o t n o t e s and are not te st e d in pr odu ct io n. ba se d on cha r act e r i zat i on , t he min i m u m an d maxim u m v a lu es r e f e r to sam p le t e st s an d re pre s ent th e me an v a lue plu s o r min u s t h re e t i mes th e sta nda rd d e viat ion ( m e an3 ). 5.1.2 t ypical v a lues unle ss ot he rwise sp ecif ied, typ i ca l d a t a ar e ba se d on t a = 25 c , v dd = 3. 3 v ( f o r t h e 1. 8 v v dd 3 . 6 v v o lt ag e r a n ge) . t h e y ar e giv e n onl y as desig n guid e lin es a n d a r e n o t t e st ed. t y p i ca l adc a c cur a cy v a lues a r e det e r min ed b y char acte r i za t i on o f a ba tch of samp les fr om a st and ar d dif f u sion lo t o v er t h e f u ll t e m per at ure r a n g e , whe r e 9 5 % of t h e d e vices h a v e an e r r o r le ss th an o r eq ual t o t he v a lu e ind i ca te d (me an 2 ) . 5.1.3 t ypical cur ves unles s otherwise s p ecified, all ty pic a l cur v es ar e giv e n o n ly as d e sign g u id eline s an d ar e no t te ste d . 5.1.4 loading capacitor th e loa d ing co ndit i on s u s e d f o r pi n par ame t e r mea s ure m en t a r e sho w n in fig u r e 16 . 5.1.5 pin input v o lta g e th e inp u t v o lta g e me asur eme n t on a p i n of t h e de vice is d e scr i b e d in f i gur e 17 . figu re 16 . p in loading c ondition s f igure 1 7 . p in inpu t v o lt a g e a i b # p & 3 4 - & p i n a i175 3 7 s tm 3 2f pin v in stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 55/147 5.1.6 p o wer suppl y sc heme figu re 18 . p o w er s uppl y sc he m e 1. 4.7f ca pacitor must be conne cted to one of the v dd pin. 5.1.7 current con sumption measurement figu re 19 . c urr e nt c ons umpt ion me asu reme nt sc h e me a i c 6 $ $ ! n a l o g 2 # s 0 , , 0 o w e r s w i t c h 6 " ! 4 ' 0 ) / s / 5 4 ) . + e r n e l l o g i c # 0 5 d i g i t a l 2 ! - " a c k u p c i r c u i t r y / 3 # + 2 4 # " a c k u p r e g i s t e r s b a c k u p 2 ! - 7 a k e u p l o g i c n & ? & 6 6 o l t a g e r e g u l a t o r 6 3 3 6 $ $ ! 6 2 % & 6 2 % & 6 3 3 ! ! $ # , e v e l s h i f t e r ) / , o g i c 6 $ $ n & ? & 6 2 % & n & ? & 6 $ $ & l a s h m e m o r y 6 # ! 0 ? 6 # ! 0 ? ? & ai14126 v bat v dd v dda i dd _v bat i dd electrical characteristics stm32f205xx, stm32f207xx 56/147 doc id 15818 rev 5 5. 2 absolute maxim u m ratings st re sse s ab o v e th e absol ut e maxim u m r a ti ngs list e d in t a b l e 7 : v o lt ag e char acte r i stics , t a b l e 8 : cu rr en t ch ar a c te r i st ics , an d t a b l e 9 : t her mal char a c te r i st ics ma y ca use per man e n t d a ma ge t o t he de vice . t hese a r e st ress r a t i ng s on ly a nd f unct i on al op er at io n of t h e de vice a t t hese con d it ion s is n o t implie d. expo su re t o ma xim u m r a t i ng co ndit i on s f o r e x te nde d per i ods ma y aff e ct de vice reliability . t a b l e 7. v o l t a g e c h ara c te ri st ic s symbol ratings m in max u nit v dd ?v ss exte r n al main sup p ly v o ltag e (i nclud i ng v dd a , v dd ) (1 ) 1. all main pow er (v dd , v dd a ) and g r ound (v ss , v ssa ) pins mu st always be connected to the external pow er supply, in the permitt ed range. tbd t bd v v in input v o ltag e on fi v e -v ol t tole r ant pin (2 ) 2. i inj( pin) must ne ver be excee ded (see t able 8 : current characteristics ) . t h i s i s impl ici t ly insur ed if v in maxi mum is respected. if v in maximum cannot be respecte d, the injection curren t must be limited externally to the i inj ( p i n ) value. a positive inje ction is indu ced by v in > v in max w h ile a negative in jectio n is induce d by v in < v ss . v ss ?0 .3 v dd +4 .0 input v o ltage on an y other pin (3 ) 3. positive current injection is not po ssible on t hese i/os. v in maximum must be respected. negative curre nt injection is possib l e an d m u st not e x ceed i inj (pin ) . v ss ?0 .3 4. 0 | v dd x | v ar i a ti on s be tw ee n d i ff e r en t v dd po w e r p i ns tbd mv |v ssx ? v ss | v a r iatio n s b e tw e en all the di ff e r ent g r ou nd pin s tbd v esd(hbm) electrostatic d i scharg e v o ltage (hu m an bod y mode l) see sect ion 5 .3 .13 : absolute max i m u m r a tings (ele ctr i cal sensitivity) t a b l e 8. curr ent c h ara c t e ri st ic s symbol ra tings max. unit i vdd t o ta l cu rrent i n to v dd /v dd a po w e r li nes (source) (1) 1. all main pow er (v dd , v dd a ) and g r ound (v ss , v ssa ) pins mu st always be connected to the external pow er supply, in the permitt ed range. tbd ma i vss t o t a l c u rre n t ou t of v ss g r ound li nes (sink) (1) tbd i io ou tp ut curren t sun k b y an y i/o a nd control pin t bd ou tp ut curren t sou r ce b y an y i/os a nd control pi n t bd i inj ( pi n) (2) 2. negat ive in jection disturbs th e analog performance of the de vice. s e e note in section 5.3 .18: 12-b i t adc characteristics . in j e cte d cu rre nt on fiv e - v olt toler a nt i/ o (3 ) 3. positive injection is not possible on these i/os. v in maximum must always be respected. i inj(pi n) mus t ne v e r be e xceeded. a nega tiv e injection is indu ced b y v in stm32f205xx, stm32f207xx electrical characteristics d o c id 158 18 re v 5 5 7/1 4 7 5. 3 operating conditions 5.3.1 general operating conditions 5. when several inputs are sub m itted to a current injection, the maximum i in j ( p i n ) is the ab solute sum of the positive and nega tive injected currents (insta n t aneous values). t hes e results are based on characterization with i in j( p i n ) maximum current injection on fo ur i/o port pins of the device. t a b l e 9. t h erma l c h a r ac te ris t i c s symb ol ra tin g s v a lu e u ni t t stg storage tempe r ature r a nge ? 40 to + 125 c t j m a xi m u m j u nc ti on t e m p e r at u r e 1 25 c t a b l e 10 . g ene r al oper a t i ng c ondit i o n s symbol p a r a meter conditions min m ax unit f hc lk inte r n al ahb cl oc k frequ ency 0 120 mhz f pcl k 1 inte r n al apb1 c l oc k freq uency 0 30 f pcl k 2 inte r n al apb2 c l oc k freq uency 0 60 v dd sta nda rd o perating v o lta g e 1 .8 (1) 1. th is va lue is reduced to 1.6 5 v for st m32f20x in wlcsp package a s suming irroff is set to v dd . 3. 6 v v dd a (2) 2. when the ad c is used, re fer to t able 59: adc characteristics . anal og ope r a tin g v o ltage (adc limited to 1 m sampl e s) must be th e same potentia l as v dd (3) 3. it is recommended to po wer v dd and v dda from the same source. a ma ximu m diffe rence of 300 mv betwe en v dd and v dda can be tolerate d during powe r-up and operation. 1.8 (1) 3. 6 v anal og ope r a tin g v o ltage (adc limited to 2 m sampl e s) 2.4 3 .6 v ba t bac kup op er a t i ng v o ltag e 1 .6 5 3 .6 v p d p o w e r dissipa ti on a t t a = 85 c f o r suffi x 6 or t a = 105 c f o r suffix 7 (4) l q fp64 444 mw wlcsp66 392 l q fp100 434 l q fp144 500 l q fp176 526 u f bga1 76 513 t a ambien t temperature f o r 6 su ff ix v e rs io n maxi m u m po w e r d i ssipa tio n ? 40 85 c lo w po w e r di ssi p a t i o n (5 ) ? 40 105 ambien t temperature f o r 7 su ff ix v e rs io n maxi m u m po w e r d i ssipa tio n ? 40 105 c lo w po w e r di ssi p a t i o n (5 ) ? 40 125 t j j unction tempe r ature r a nge 6 suffix v e rsion ? 40 105 c 7 suffix v e rsion ? 40 125 electrical characteristics stm32f205xx, stm32f207xx 58/147 doc id 15818 rev 5 4. if t a is lower, h i gher p d values are a l lowed as long as t j does n o t exceed t j max. 5. in low pow er dissipatio n state , t a can be extended to this range as lon g as t j doe s not exceed t j max. t a b l e 11. limita tions d e pe nding on th e ope rat i n g po wer s uppl y r a ng e op eratin g po w e r suppl y ra n g e adc op era t io n maxim u m flash me mor y a cce ss frequenc y (f fl ashm a x ) nu mber o f wait state s at maxi m u m cpu frequenc y (f cpu m a x = 12 0 m h z ) (1) i/o o p erati o n fsmc contr o lle r op era t i o n p o ssib l e fl ash memor y op era t io ns v dd =1.8 t o 2.1 v (2 ) con v ersion time up to 1 m sps 16 mhz with no flash me m o r y w a it state 7 (3) ? d eg r a ded spee d perf o r m an ce ? n o i /o compen sa ti on up t o 30 mh z 8- bi t er a se a nd prog r a m o perati ons on l y v dd = 2.1 to 2.4 v con v ersion time up to 1 m sps 18 mhz with no flash me m o r y w a it state 6 (3) ? d eg r a ded spee d perf o r m an ce ? n o i /o compen sa ti on up t o 30 mh z 16 -b i t e r as e a nd prog r a m o perati ons v dd = 2.4 to 2.7 v con v ersion time up to 2m sp s 24 mhz with no flash me m o r y w a it state 4 (3) ? d eg r a ded spee d perf o r m an ce ? i /o compen sa ti on wo r ks up t o 48 mh z 16 -b i t e r as e a nd prog r a m o perati ons v dd = 2.7 to 3.6 v (4 ) con v ersion time up to 2m sp s 30 mhz with no flash me m o r y w a it state 3 (3) ? f u ll-spee d ope r a tion ? i /o compen sa ti on wo r ks ?u p t o 60 mhz wh e n v dd = 3.0 to 3.6 v ?u p t o 48 mhz wh en v dd = 2.7 to 3.0 v 32 -b i t e r as e a nd prog r a m o perati ons 1. th e number of wait sta tes can be reduced by reducing the cpu frequency (see figure 2 0 ). 2. th is vo ltage range is reduced to 1.6 5 to 2.1 v for devices in wlcsp package assuming ir rof f is set to v dd . 3. th anks to the a r t accelerator an d the 128-bit f l a s h memory , the number of wait states g i ven here does not impact the execution speed from f l ash memory since th e art accelerator a l lows to achieve a performan ce eq uivalent to 0 wait state program executio n. 4. th e voltage range for ulpi usb high-speed, e t h e rnet mii a nd ethernet rmii is 3.0 to 3.6 v . stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 59/147 figu re 20 . n umbe r of wa it st at es ve r s us f cp u a nd v dd rang e 5.3.2 operating conditions at po wer - up / po wer - do wn (regulator not b ypassed) su bject t o g ene r a l op er a t in g cond itio ns f o r t a . t a b l e 12 . o per a ting c ondition s at p o wer - up / po wer - d o wn (re gulat or not b y p ass ed) a i 0 1 2 3 4 5 6 7 8 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64 68 72 76 80 84 88 92 96 10 0 10 4 10 8 11 2 11 6 12 0 number of wait states f c pu (m h z ) w a i t s t a t es vs f c pu a nd v dd r a ng e 1.6 5 t o 2. 1v 2. 1 t o 2. 4v 2. 4 t o 2.7v 2. 7 t o 3.6v symbol p a ra meter m in max u nit t vdd v dd r i s e ti me rat e t b d s/ v v dd fall time rate tbd electrical characteristics stm32f205xx, stm32f207xx 60/147 doc id 15818 rev 5 5.3.3 operating conditions at po we r - up / po wer - do wn in regulator b ypass mode su bject t o g ene r a l op er a t in g cond itio ns f o r t a . t a b l e 13 . o per a ting c ondition s at p o wer - up / po wer - d o wn in re gulat or by p a s s m o d e 5.3.4 embed ded reset and po wer contr o l b l oc k c haracteristics th e pa r a me t e rs giv e n in ta b l e 1 4 a r e de r i v e d f r o m te sts p e r f o r m e d un de r am b i en t t e m per a t ure and v dd su pply v o lt ag e co ndit i o n s sum m ar iz ed in ta b l e 1 0 . symbol p a rameter c onditions m in max u nit t vdd v dd r i se ti me rat e p o w e r - u p t b d s/v v dd f a ll time r a te p o w e r- do wn tbd t vc ap v cap_1 an d v cap_ 2 r i se time r a te po w e r - u p t b d v cap_1 an d v cap_ 2 fa l l time r a te po w e r - d o w n t b d t a b l e 14 . e mbe d ded re set and po w e r con t r o l b l oc k c h ar act er is ti cs symbol p a r a meter c onditions m in t y p max u nit v pvd pro g r a mmab l e v o ltage detector le v e l sele ctio n pls[2 : 0 ] = 000 (r i s i ng edg e) tbd t bd tbd v pls[2 : 0 ] = 000 (f a llin g edge ) t bd 2.00 tbd v pls[2 : 0 ] = 001 (r i s i ng edg e) tbd t bd tbd v pls[2 : 0 ] = 001 (f a llin g edge ) t bd 2.20 tbd v pls[2 : 0 ] = 010 (r i s i ng edg e) tbd t bd tbd v pls[2 : 0 ] = 010 (f a llin g edge ) t bd 2.30 tbd v pls[2 : 0 ] = 011 (r i s i ng edg e) tbd t bd tbd v pls[2 : 0 ] = 011 (f a llin g edge ) t bd 2.50 tbd v pls[2 : 0 ] = 100 (r i s i ng edg e) tbd t bd tbd v pls[2 : 0 ] = 100 (f a llin g edge ) t bd 2.70 tbd v pls[2 : 0 ] = 101 (r i s i ng edg e) tbd t bd tbd v pls[2 : 0 ] = 101 (f a llin g edge ) t bd 2.80 tbd v pls[2 : 0 ] = 110 (r i s i ng edg e) tbd t bd tbd v pls[2 : 0 ] = 110 (f a llin g edge ) t bd 2.90 tbd v pls[2 : 0 ] = 111 (r i s i ng edg e) tbd t bd tbd v pls[2 : 0 ] = 111 (f a llin g edge ) t bd 3.00 tbd v v pvdhyst (2) pvd hysteresis 100 mv stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 61/147 5.3.5 suppl y current c haracteristics th e cur r en t con s u m pt ion is a f unct i on o f se v e r a l par ame t e r s and f a ct or s such a s t he o per at ing v o lt ag e , am bien t t e m per at ure , i/ o p i n load ing , de vi ce sof t w ar e conf ig ur at io n, o per at ing f r e que ncies , i / o p i n s w it chin g r a t e , pr og r a m locat i o n in mem o r y an d e x ecut ed binar y code . th e cur r en t con s u m pt ion is me asur ed as de scr i be d in fig u re 19: cu rr en t consu m pt ion me asur eme n t sche me . all r u n mod e cur r ent con sump t io n m easur em ent s g i v e n in t h is se ct ion ar e per f o r m ed with a r e d u ced cod e th at g i v e s a co nsump t io n eq uiv a le nt t o dhr yst on e 2. 1 code . v por/pdr p o w e r-on/po w e r-do w n reset threshold f a lli ng ed ge tbd (1 ) 1.70 tbd v rising e dge tbd 1 .74 t bd v v bor1 bro w nou t le v e l 1 th reshol d f a lli ng ed ge tbd 2 .20 t bd v rising e dge tbd t bd tbd v v bor2 bro w nou t le v e l 2 th reshol d f a lli ng ed ge tbd 2 .50 t bd v rising e dge tbd t bd tbd v v bor3 bro w nou t le v e l 3 th reshol d f a lli ng ed ge tbd 2 .80 t bd v v p d r h yst (2) pdr h ysteresis 40 mv t rs t t em po (2 ) reset te mp or izatio n t bd tbd t bd ms i ru s h in rush current on v o ltag e regul ato r po w e r-on -- 2 0 0 m a 1. th e product beha vior is guarante ed by design dow n to the minimum v por / pdr val u e. 2. guarante ed by design, not tested in production . t a b l e 14 . e mbe d ded re set and po w e r con t r o l b l oc k c h ar act er is ti cs ( c on ti n u ed ) symbol p a r a meter c onditions m in t y p max u nit electrical characteristics stm32f205xx, stm32f207xx 62/147 doc id 15818 rev 5 t y p i c a l a nd maxi m u m current con s umption th e mcu is place d und er t h e f o llo win g co nd itio ns: all i/ o pin s a r e in in put mod e with a st at ic v a lue at v dd or v ss ( n o lo ad) . all per ip her als a r e d i sab l ed e xcep t if it is e x plic itly mentioned. the flas h access t i me is adj uste d to f hclk f r equ en cy (0 w a it st at e f r om 0 t o 3 0 mhz, 1 w a i t st at e f r om 3 0 t o 60 mhz, 2 w a it st at es f r o m 6 0 t o 9 0 mhz and 3 w a it sta t es fr om 90 to 1 2 0 mh z). pre f e t ch a nd cache o n ( r e m ind e r : t h is bit m u st be set bef or e cloc k se tt in g and b u s prescaling). when t h e per ip he r a ls are ena b l e d f pc lk1 = f hclk /4 , f pclk 2 = f hclk /2 , f adcc lk = f pc lk2 /4 the maxim u m v a lues ar e o b t a ine d f o r v dd = 3 . 6 v a nd ma xim u m am bien t t e m per a t ure (t a ), and t h e typica l v a lu es f o r t a = 25 c an d v dd = 3. 3 v u n le ss ot he rw ise sp ec ifie d. t a b l e 15. t y pica l and ma xim u m cur r ent cons umpt io n in run mode , c ode wit h dat a pr oce s s i ng ru nning fr om flash symb ol p ara meter c on di ti on s f hc lk ty p i c a l m a x (1) unit t a = 25 c t a = 85 c t a = 10 5 c i dd su ppl y cu rre nt in run mode exter nal clo c k (2) , al l p e r i ph er a l s enab led 1 20 mhz t bd tbd t bd ma 90 m h z t b d tbd t bd 60 m h z t b d tbd t bd 30 m h z t b d tbd t bd 26 m h z t b d tbd t bd 16 m h z t b d tbd t bd exter nal clo c k (2) , all p e r ipher a ls disab led 1 20 mhz t bd tbd t bd 90 m h z t b d tbd t bd 60 m h z t b d tbd t bd 30 m h z t b d tbd t bd 26 m h z t b d tbd t bd 16 m h z t b d tbd t bd 1. based on characterization, not tested in prod uction. 2. external clock is 8 mhz and pll is on when f hcl k > 8 mhz. stm32f205xx, stm32f207xx electrical characteristics d o c id 158 18 re v 5 6 3/1 4 7 t a b l e 16. t y pica l and maxim u m cur r ent cons umpt io n in run mode , c ode wit h dat a pr oce s s i ng run n in g fr om ram symb ol p a ramet e r c on di tion s f hc lk ty p m a x (1) unit t a = 25 c t a = 85 c t a = 10 5 c i dd suppl y cu rrent i n run mode exter nal cloc k (2 ) , al l per i pherals ena b l e d (3 ) 1 20 mhz 49.5 t bd tbd ma 90 mh z 3 8 t bd tbd 60 mh z 2 6 t bd tbd 3 0 mhz 14.5 t bd tbd 26 mhz t bd tbd t bd 16 mhz t bd tbd t bd exter nal cloc k (2) , all pe r ipher a ls d isab l ed 1 20 mhz 2 2 t bd tbd 90 mh z 1 7 t bd tbd 6 0 mhz 12.5 t bd tbd 30 mh z 7 t b d t bd 26 mhz t bd tbd t bd 16 mhz t bd tbd t bd 1. based on characterization, tested in production at v dd max, f hclk max. 2. external clock is 8 mhz and pll is on when f hcl k > 8 mhz. 3. add an a dditional power co nsumption of 0.8 ma per adc for the analo g part. in appl icatio ns, this con s umption occurs only while the adc is on (adon bit is set in the adc_ cr2 register). t a b l e 17. t y pi ca l and maxi m u m cur r ent cons umpt io n in sl eep mod e symbol p a ra meter conditions f hclk typ max (1) un it t a = 25 c t a = 8 5 c t a = 10 5 c i dd su ppl y curren t in sl eep mod e ex te r n al cl oc k (2) , all pe r i ph er a l s e nab led (3) 1 20 mhz 3 7 . 5 t bd tbd ma 90 m h z 2 9. 5 t bd tbd 60 m h z 2 0. 5 t bd tbd 30 m h z 1 4. 5 t bd tbd 26 m h z t bd tbd t bd 16 m h z t bd tbd t bd ex ter n al cloc k (2 ) , a ll per i pherals disa b l ed 1 20 mhz 8 .0 tbd t bd 90 m h z 6 .5 t b d t bd 60 m h z 5 .0 t b d t bd 30 m h z 3 .5 t b d t bd 26 m h z t bd tbd t bd 16 m h z t bd tbd t bd 1. based on characterization, tested in production at v dd ma x and f hclk max wit h periphera l s enabled. 2. external clock is 8 mhz and pll is on when f hcl k > 8 mhz. electrical characteristics stm32f205xx, stm32f207xx 64/147 doc id 15818 rev 5 3. add an additional po wer consumptio n o f 0.8 ma pe r adc for th e analo g part. in applications, th is consump t ion occurs only while the adc is on (adon bit is set in the adc_ cr2 register). t a b l e 18. t y pica l and ma xim u m cur r ent cons umpt io ns in st op mode symbol p a ra meter c onditions ty p (1 ) max unit v dd /v ba t = 1. 8 v v dd /v ba t = 2. 4 v v dd /v ba t = 3. 3 v t a = 85 c t a = 10 5 c i dd _st o p supply cur rent in st o p mo de wi t h ma in reg u l at or i n r un mode fl ash in stop mo de , l o w-speed a nd hig h -spee d inter nal r c oscil l ators and h i gh-sp eed oscil l ator off (no ind epe nden t w a tchdo g) 350 tbd t bd a fl ash in dee p po w e r d o wn mode , l o w-spe ed and h i gh -sp eed in te r na l rc oscill ators a nd hig h -spee d oscill ator off (no ind epen den t w a tchdog ) 300 tbd t bd supply cur rent in st o p mo de wi t h ma in reg u l at or i n lo w p o w e r mode fl ash in stop mo de , l o w-speed a nd hig h -spee d inter nal r c oscil l ators and h i gh-sp eed oscil l ator off (no ind epe nden t w a tchdo g) 200 fl ash in dee p po w e r d o wn mode , l o w-spe ed and h i gh -sp eed in te r na l rc oscill ators a nd hig h -spee d oscill ator off (no ind epen den t w a tchdog ) 150 1. typica l valu es are measured at t a = 25 c. t a b l e 19. t y pi ca l and ma xi m u m cur r ent cons umpt io ns i n st an db y mod e symbol p a ra meter c onditions ty p (1 ) max unit v dd /v ba t = 1. 8 v v dd /v ba t = 2. 4 v v dd /v ba t = 3. 3 v t a = 85 c t a = 10 5 c i dd _st b y supply cur rent i n stan db y mode bac kup sram on, r t c on 4 t bd (2 ) tbd (2) a bac kup sram off , r t c on 3.3 t bd (2 ) tbd (2) bac kup sram on, r t c off 3 .2 tbd (2 ) tbd (2) bac kup sram off , r t c off 2 .5 tbd (2 ) tbd (2) 1. typica l valu es are measured at t a = 25 c. 2. based on characterization, not tested in prod uction. stm32f205xx, stm32f207xx electrical characteristics d o c id 158 18 re v 5 6 5/1 4 7 on-c hip pe ri pheral current c onsumpti o n th e cur r en t con s u m pt io n of t h e on- chip p e r i ph er a l s is giv e n in ta b l e 2 1 . th e mcu is place d under the f o llo wing conditions : all i / o p i ns ar e in inpu t mo de wit h a sta t ic v a lue at v dd or v ss (n o loa d ) all pe r i ph er a l s ar e disab l e d unle s s ot he rwise men t io ne d t he giv e n v a lue i s calculat e d b y mea s u r ing t h e cu rr ent co nsum pt ion ? w it h all p e r i ph er a l s cloc k e d of f ? w it h on e pe r i phe r a l cloc k e d on ( w it h o n ly t h e clo c k ap plie d) am bien t op er a t in g t e mp er a t u r e a nd v dd su pp ly v o lt ag e co nd itio ns su m m a r iz ed in ta b l e 7 . t a b l e 20. t y pi ca l and ma xi m u m cur r ent cons umpt io ns i n vb a t mode symbol p a ra meter c onditions ty p (1 ) max unit v dd /v ba t = 1. 8 v v dd /v ba t = 2. 4 v v dd /v ba t = 3. 3 v t a = 85 c t a = 10 5 c i dd _vb a t bac k up d o main suppl y cur r ent bac kup sram off , lo w-speed oscill ator a nd r t c on 0. 8 t bd (2 ) tbd (2) a bac kup sram on, r t c on 1.5 t bd (2 ) tbd (2) bac kup sram off , r t c off 0 tbd (2 ) tbd (2) bac kup sram on, r t c off 0 .7 tbd (2 ) tbd (2) 1. typica l valu es are measured at t a = 25 c. 2. based on characterization, not tested in prod uction. t a b l e 21 . p e r ip hera l c u rre nt co nsump t ion p e ripher al (1) t y pical consumption at 25 c unit ahb1 g p io a t b d ma g p io b t b d g p io c t b d g p io d t b d g p io e t b d g p io f t b d g p io g t b d g p io h t b d g p io i t b d ot g _ h s t b d eth_m a c t b d ahb2 ot g _ f s t b d dcmi t bd rng tbd electrical characteristics stm32f205xx, stm32f207xx 66/147 doc id 15818 rev 5 apb1 ti m2 t b d ma tim3 t b d tim4 t b d tim5 t b d tim6 t b d tim7 t b d ti m12 t bd ti m13 t bd ti m14 t bd usar t2 tb d usar t3 tb d ua r t 4 t b d ua r t 5 t b d i2 c1 t b d i2 c2 t b d i2 c3 t b d spi2 t b d spi3 t b d can1 tbd can2 tbd da c t b d apb2 sdio tb d ma tim1 t b d tim8 t b d tim9 t b d ti m10 t bd ti m11 t bd adc1 (2) tb d adc2 (2) tb d adc3 tbd spi1 t b d usar t1 tb d usar t6 tb d 1. f hclk = 120 m h z, f apb1 = f hc l k /4, f apb2 = f hcl k /2, default pre s caler value for each periphe ral. 2. specific conditions for a d c: f hclk = 12 0 m h z , f apb1 = f hc l k /4, f apb2 = f hclk /2, f adcclk = f apb2 /2 , ad on bit in t he adc_cr 2 register is set to 1 . t a b l e 21 . p e r ip hera l c u rre nt co nsump t ion (c ont in u e d) p e ripher al (1) t y pical consumption at 25 c unit stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 67/147 5.3.6 external c l oc k sour ce c haracteristics high-s p eed e x te rn al user c l oc k g e nerated fr om a n e x ternal s our c e th e char acte r i st ics g i v en in ta b l e 2 2 re sult f r om t e sts pe rf or m ed u s in g an h i gh- spee d e x t e r n a l cloc k so ur ce , an d und er a m bie n t t e mpe r at ur e an d su pply v o lt ag e co nd itio ns summar iz ed in ta b l e 1 0 . lo w-speed e x ternal us er c l oc k g e ne ra ted fr o m an e x te rn al sour ce th e char acte r i st ics g i v en in ta b l e 2 3 re sult f r om t e sts pe rf or m ed u s in g an lo w-spe e d e x t e r n a l cloc k so ur ce , an d und er a m bie n t t e mpe r at ur e an d su pply v o lt ag e co nd itio ns summar iz ed in ta b l e 1 0 . t a b l e 22 . h i gh- spe e d e x t e rn al u ser c l oc k c h ara c t e ri st i c s symbol p a rame ter c onditions m in t y p m a x u n it f hse_ e xt exte r n al user cloc k so urce fre que ncy (1 ) 18 5 0 m h z v hseh osc_ in in put pin hi gh le v e l v o ltage 0 . 7 v dd v dd v v hsel osc_ in in put pin lo w le v e l v o ltage v ss 0.3v dd t w(hse) t w(hse) osc_ in hi gh or lo w time (1 ) 1. guarante ed by design, not tested in production . 16 ns t r(h se) t f ( hse) osc_ in r i se o r f a ll ti me (1 ) 20 c in(hse) osc_ in in put capaci t an ce (1 ) 5p f duc y ( h se) duty cycle 4 5 5 5 % i l osc_ in inpu t le akage curren t v ss v in v dd 1 a t a b l e 23 . l o w -s pee d e x te rnal use r c l oc k c h a r ac te ris t i c s symb ol p a rameter c on dit i on s m in t y p m ax un it f lse_ e xt use r exter nal cloc k source frequ ency (1) 1. guarante ed by design, not tested in production . 32.76 8 100 0 khz v l seh osc32_ in in put pin hi gh le v e l v o ltage 0.7 v dd v dd v v lsel osc32_ in in put pin lo w le v e l v o ltage v ss 0.3v dd t w(l se) t w(l se) osc32_ in hi gh or lo w ti me (1 ) 45 0 ns t r(l se) t f(lse) o s c32_ in r i se o r f a ll ti me (1 ) 50 c in( l se) osc32_ in in put ca paci t an ce (1 ) 5p f ducy (lse ) duty cycle 3 0 7 0 % i l osc32_ in inpu t leaka ge current v ss v in v dd 1 a electrical characteristics stm32f205xx, stm32f207xx 68/147 doc id 15818 rev 5 figu re 21 . h igh- spe e d ex te rnal c l oc k s our ce a c timing dia g ra m figu re 22 . l o w -s pee d e x te rnal c l oc k s our ce a c timing dia g ra m high-s p eed e x te rn al c l oc k g e nerated fr om a c r ystal/c era m ic reso nator the high-speed external (hse) clock can be supplied with a 4 to 26 mhz crystal/ceramic resonator oscillato r. all the information given in this paragraph are based on characterization results obtained with typical external components specified in ta bl e 2 4 . in the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion a nd startup stabilization time. refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). a i1752 8 o s c_in extern a l s tm 3 2f clock s o u rce v h s eh t f(h s e) t w(h s e) i l 90 % 10 % t h s e t t r(h s e) t w(h s e) f h s e_ext v h s el a i17529 o s c 3 2_ i n extern a l s tm 3 2f clock s o u rce v l s eh t f(l s e) t w(l s e) i l 90 % 10 % t l s e t t r(l s e) t w(l s e) f l s e_ext v l s el stm32f205xx, stm32f207xx electrical characteristics d o c id 158 18 re v 5 6 9/1 4 7 fo r c l1 a nd c l2 , it is re co mme nde d t o use hig h - qua lity e x t e r n al ce r a m i c cap a cito rs in th e 5 p f to 2 5 pf r a nge (t yp .) , d e signe d f o r h i gh- f r e que ncy a pplicat io ns , a n d sele cte d to m a t c h th e re qu ire m en ts o f th e cr yst al or re so n a t o r (s ee figu re 2 3 ). c l1 a nd c l2 are usually t he sa me s i z e . th e cr y s ta l m a n u f a ct ur er ty pic a lly spe c if ie s a loa d capa cit a nce wh ich is t he ser i e s co mbin at ion o f c l1 an d c l2 . pcb and mcu p i n cap a cita nce m u st be include d ( 1 0 p f can b e used a s a r o u gh est i mat e o f t he comb ine d pin an d bo ar d ca pa cit a n c e ) when sizing c l1 an d c l2 . ref e r to the applic ation note an28 67 ?oscillator design guide f o r st micr ocon tr olle rs? a v ailab l e f r om t h e st we bsit e www . s t. co m. fi gu re 23 . t ypi c a l appli c ati on w i t h an 8 mhz cr y s t a l 1. r ext value depen ds on the cr ystal characteristics. lo w-speed e x ternal c l oc k g e nerated fr om a cr ysta l/ceramic re sonator th e lo w-spe ed e xt e r nal ( l se) cloc k ca n be sup p lied wit h a 32 .7 68 khz cr ysta l / c e r amic resonator oscillato r . all the inf o r m ation giv e n in this par a g r aph are bas e d on c h ar acter i z a tion r e sult s o b t a in ed with typical e x t e r nal comp on ent s sp ecifie d in ta b l e 2 5 . in th e ap p l ic at ion , the resonator and the load capac i tors ha v e to be placed as close as possib le to the os cillator pins in order to minimiz e output distor tion a nd star tup s t abilization time . ref e r to the cr ys tal r eson at or m an uf act ur er f or mor e de ta ils on th e re so nat or ch ar a c t e r i st ics ( f r eq uen cy , p a c kag e , accur a cy). t a b l e 24 . h se 4-2 6 mhz os ci l l a t or c h ara c te ri st ic s (1) (2 ) 1. resonator ch aracte rist ics g i ven by the crystal/ ceramic resonator manufacturer. 2. based on characterizatio n , not tested in prod uction. symb ol p a rameter c on di tion s m in t y p m ax uni t f osc_ in osci llator fre que ncy 4 2 6 mhz r f f e e dbac k resistor 2 0 0 k c reco mmen ded load capa citance v e rsu s eq uiv a lent ser i a l resistance of the cr ystal ( r s ) (3) 3. th e relatively low value of the r f re sisto r offers a g ood prot ection against issues resulting from use in a humid environment, due to the induced lea k age and t he bias cond ition change. ho weve r, it is recommend ed to take this point into acco unt if the mcu is used in tou gh humidity conditions. r s = 30 30 p f i 2 hse dr ivin g current v dd = 3.3 v , v in =v ss w i th 3 0 pf lo ad 1m a g m osci llator transco nductan c e s ta r t up 25 ma/v t su(hse (4 ) 4. t su(h s e ) is th e startup time measured f r om the mome nt it is enabled (by software) to a stabilized 8 mhz oscillation is reached. this value is measured for a sta ndard crystal resonat or an d it can vary significan t ly with the crystal man ufactu r er star tu p time v dd is stabi liz ed 2 m s a i175 3 0 o s c_ou t o s c_in f h s e c l1 r f s tm 3 2f 8 mh z re s on a tor re s on a tor with integr a ted c a p a citor s bi as controlled g a in r ext (1) c l2 electrical characteristics stm32f205xx, stm32f207xx 70/147 doc id 15818 rev 5 no te : f or c l1 a nd c l2 it is re co mm e n d e d to us e hig h - q ua lity e x ter n al ce r a m i c c a p a c i to rs in th e 5 p f to 1 5 pf r a nge se lecte d t o mat c h th e re qu irem ent s of t h e cr yst a l or r e son a t o r (see fig u r e 24 ). c l1 and c l2, ar e usua lly t h e sa me siz e . th e cr yst a l ma n u f a ct ur er t y pically spec ifies a load capac i tance w h ic h is t he ser i e s comb ina t io n of c l1 and c l2 . l oad ca pacit ance c l has th e f o llo wing f o r m u l a: c l = c l1 x c l2 / ( c l1 + c l2 ) + c str a y wher e c str a y is th e pin cap a cita nce an d bo ar d or t r ace pcb-related c a pac i tanc e . t ypically , it is b e t w ee n 2 pf a nd 7 p f . caut ion: t o a v oi d e xce ed ing t he ma xim u m v a lue o f c l1 an d c l2 (1 5 pf ) it is st ro ng ly r e com m e nd ed t o use a r e son a t o r wit h a loa d ca pa cit a n c e c l 7 pf . ne v e r u se a re so na to r with a lo ad cap a cit ance of 12 .5 p f . ex ampl e: if y o u cho o se a reso nat or wit h a lo ad capa cita nce of c l = 6 pf , an d c str a y = 2 pf , th en c l1 = c l2 = 8 pf . fi gu re 24 . t ypi c a l ap pli c ati o n w i t h a 32 .7 68 k h z cryst al t ab l e 25 . l se os ci ll at or c h a r ac te ris t i cs (f ls e = 32. 7 68 khz) (1) 1. based on characterizatio n , not tested in prod uction. symb ol p a rameter c on di tio n s m i n t y p m ax un it r f f eed bac k resistor 5 m c (2 ) 2. refer to the no te and caution parag raphs below the tab l e , an d to the application note a n 2867 ?oscillator design guid e for st microcontrollers?. recommen ded lo ad capa citance v e rsus equ iv al ent se r i al resistance of th e cr ystal (r s ) (3) 3. th e oscillator select ion can be o ptimized in t erms of supply current using an hi gh quality resonator wit h smal l r s value for e x ample msiv-t in32.768khz. refe r to crysta l manuf acturer for more details r s = 3 0 k 15 pf i 2 lse dr ivin g cu rrent v dd = 3. 3 v , v in = v ss 1.4 a g m oscil l ator t r anscon ductance 5 a/v t su( l se) (4 ) 4. t su(lse) is the startup t i me measured from th e mom ent it is enabled (by softwa r e) to a sta b ilized 32.768 khz oscillation is reached. th is va lue is measu r ed for a standard cr ystal resonator a nd it can vary significantly with t he crystal manufa c turer st ar tup time v dd is stabil i z e d 3 s a i175 3 1 o s c 3 2_ou t o s c 3 2_i n f l s e c l1 r f s tm 3 2f 3 2.76 8 kh z re s on a tor re s on a tor with integr a ted c a p a citor s bi as controlled g a in c l2 stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 71/147 5.3.7 internal c l oc k sour c e c h aracteristics th e pa r a me t e rs giv e n in ta b l e 2 6 a r e de r i v e d f r o m te sts p e r f o r m e d un de r am b i en t t e m per at ure and v dd su pply v o lt ag e co ndit i o n s sum m ar iz ed in ta b l e 1 0 . high-speed int e rn al (hsi) rc oscillator lo w-speed internal (l si) rc oscillator 5.3.8 w a keup time fr om lo w-po wer mode th e w a k e up t i mes g i v en in ta b l e 2 8 is m e as ur ed on a w a k e up p h a se with a 16 m h z hsi rc os cillator . the cloc k source used to w a k e up the de vic e depe nds from the current oper ating mo de : stop or s t andb y mode: the cloc k source is the rc os cillator sle e p m o de : th e c l oc k so ur ce is th e cloc k th a t w a s se t be f o re e n t er in g sle e p m o de . all t i ming s ar e de r i v ed f r o m te st s p e r f o r me d un der amb i ent te mpe r at u r e an d v dd supply v o l t a ge con d it ions su mma r i z e d in ta b l e 1 0 . t a b l e 26 . h si o sci l l a t or c h ara c t e ri st ic s (1) 1. v dd = 3.3 v , t a = ?40 to 1 0 5 c un less otherwise sp ecified . symb ol p ar amete r c on d i ti on s m in t y p m a x un it f hsi f r equ ency 1 6 mh z ac c hsi accur a cy of the hsi oscillator u s e r -tr i mmed wi th the rcc _cr re gister (2 ) 2. refer to application note an28 68 ?stm3 2 f10xxx interna l rc oscillator (hsi) calibra t ion? available from the st w ebsite ww w.st.com. tbd % f a ctor y- ca librated t a = ?4 0 to 10 5 c t bd tbd % t a = ?1 0 to 85 c tbd t bd % t a = 0 to 70 c tb d t bd % t a = 25 c tb d t bd % t su(h si) hsi oscilla to r star tup ti me tb d t bd s i dd (h si) hsi oscilla to r po w e r consu m p t i o n 80 tbd a t a b l e 27 . l si osc i l l a t o r c h a r act er is ti cs (1) 1. v dd = 3 v , t a = ?40 to 10 5 c unless ot herwise spe c ified . sy mb ol p a ra m e te r m in t y p m a x un it f lsi (2) 2. based on characterizatio n , not tested in prod uction. f r e quen cy 3 0 3 2 60 khz t su(l si) (3) 3. guarante ed by design, not tested in production . lsi oscil l ator sta r tup time 8 5 tbd s i dd (ls i ) (3 ) lsi oscil l ator po w e r co nsumption 0 .65 t bd a electrical characteristics stm32f205xx, stm32f207xx 72/147 doc id 15818 rev 5 5.3.9 pll c haracteristics th e pa r a me t e rs giv e n in ta b l e 2 9 and ta b l e 3 0 a r e d e r i v e d f r om t e sts per f o r m ed un de r t e m per a t ure and v dd su pply v o lt ag e co ndit i o n s sum m ar iz ed in ta b l e 1 0 . t a b l e 28 . l o w -po w er mode w ake up ti mi ngs symbol p a ra meter t y p unit t wus l eep (1 ) 1. th e wakeup times are measured from the w a keu p even t to the point in which the user application code rea d s the fir s t instructio n. w ak e up fro m slee p mo de 1 s t wu st op (1) w a k e up fro m stop mode (regu lator in r u n mod e ) 9 s w a k e up fro m stop mode (regu lator in lo w po w e r mo de ) 1 5 w a k e up fro m stop mode (regu lator in lo w po w e r mo de and flash memor y in de ep po w e r do wn mode ) 11 0 t wu stdby (1) w a k e up fro m standb y mod e 2 0 0 s t a b l e 29. ma i n pll c h ara c t e ri st ic s symbol p a rame te r c onditions m in (1) ty p (1 ) max (1 ) unit f pll _ in pl l inpu t cloc k (2) 0.95 1 2 .00 m h z f pll _ out pl l m u ltip lier outpu t cloc k 2 4 1 2 0 mh z f pll4 8_ ou t 4 8 mhz pll m u lti p lie r ou tp ut clo c k 4 8 m h z f vc o_ out pl l vc o outpu t 192 43 2 m h z t lo ck pl l l o c k time 35 0 s jitter cy cle-to-c ycle jitter system c l oc k 120 mhz 300 p s i dd (pll ) pl l p o w e r con s umption on vdd vc o fre q = 192 mhz vc o fre q = 432 mhz tb c t bc ma i dd a(pll) pl l p o w e r con sumption on vdd a vc o fre q = 192 mhz vc o fre q = 432 mhz tb c t bc ma 1. based on characterization, not tested in prod uction. 2. ta ke care of using th e approp ria te division factor m to obtain the specified pll input clock va lues. the m facto r is share d betw een pll a nd plli2 s . t a b l e 30. pll i 2 s (aud io pll) c h ar act eri s t i cs symbol p a rame te r c onditions m in (1) ty p (1 ) max (1 ) unit f p l li2s _ i n plli2s i nput cloc k (2 ) 0.95 1 1 .05 m h z f plli 2 s _o ut pl li2s m u ltipl i er output cloc k 2 1 6 mh z f vc o_ out pl li2s vco output 192 43 2 m h z t lo ck pl li2s loc k time 35 0 s jitter cy cle-to-c ycle jitter system c l oc k 120 mhz 300 p s stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 73/147 5.3.10 pll spread spectrum c l oc k g eneration (sscg) c haracteristics th e spr ead spe ctr u m clo c k ge ne r a t i on ( sscg ) f eat u r e is only a v a ilab l e on t h e main pll . equation 1 the frequency mo dulation per i od (modeper) is gi v en b y the equation belo w : equation 2 jitter master i2s cloc k jitter cy cle to cycle at 1 2 ,343 khz o n 48khz per iod n = 43 2, p= 4, r= 5 tbc t bc p s jitter master i2s cloc k jitter a v er ag e fre quen cy of 1 2 ,343 khz n = 43 2, p= 4, r= 5 o n 256 sampl e s tbc t bc p s jitt er ws i2s cloc k j i tter cy cle to cycle at 48 khz o n 100 0 sa mp les tbc t bc p s jitte r mai n cloc k ou tp ut f o r ether net cy cle to cycle at 50 mhz o n 100 0 sa mp les tbc t bc p s jitt er bit t i m e can jitter cy cle to cycle at 1 m hz o n 100 0 sa mp les tbc t bc p s i dd (pll i2 s) pl li2s po w e r con sumption on v dd vc o fre q = 192 mhz vc o fre q = 432 mhz tb c t bc ma i dd a( pll i 2 s ) pl li2s po w e r con sumption on v dd a vc o fre q = 192 mhz vc o fre q = 432 mhz tb c t bc ma 1. based on characterization, not tested in prod uction. 2. ta ke care of using th e approp ria t e division factor m to have the specified pll input clock values. t a b l e 30. pll i 2 s (aud io pll) c h ar act eri s t i cs ( c on ti n u ed) symbol p a rame te r c onditions m in (1) ty p (1 ) max (1 ) unit table 31 . sscg pa ramet e r s co nst r ai nt sym b ol p a rame ter m in t y p m a x unit f mo d modu lation frequ ency 1 0 k hz md p e a k mod u la tion depth 0 .5 2 dec m o deper * incs tep 2 15 ? 1 dec m o d e p e r r ound f pll_ in 4f mod () ? [] = electrical characteristics stm32f205xx, stm32f207xx 74/147 doc id 15818 rev 5 eq uat ion 2 a llo ws t o ca lculat e t he in cr eme n t st ep ( i ncstep) : an a m plit ud e qu ant izat ion e r r o r m a y b e gen er a t ed be ca use t he lin ear mod u lat i on p r o f ile is o b t a ine d b y t a king t h e q u a n t i z e d v a lues (r ou nde d to th e nea re st int e g e r ) of modper an d i n cstep . as a r e sult , t h e a c h i e v ed m odu lat i on d ept h is qua nt iz ed . th e pe rcen ta ge q uan tiz ed mo du lat i on de pt h is g i v en b y t h e f o llo wing f o r m ula : fig u r e 25 a nd fig u r e 26 sho w th e main pl l ou tp ut cloc k w a v e f o r m s in cen t e r spr ead a n d do wn sp re ad m o de s , w h e r e : f0 is f pll_out no m i na l. t mode is t he mo dula t ion pe r i od . md is th e mod u la tio n dep t h . figu re 25 . p ll o u tp ut c l o c k wa vef or ms in c e nt er sp rea d mo de figure 26. pll output clock waveforms in down spread mode i n c s t e p r ou nd 2 15 1 ? () md f vco _ o u t () 10 0 5 modeper () ? [] = md quan ti ze d % m odep er incstep 100 5 () 2 15 1 ? () f vco _ o u t () ? = & r e q u e n c y 0 , , ? / 5 4 4 i m e & t m o d e t m o d e m d a i m d & r e q u e n c y 0 , , ? / 5 4 4 i m e & t m o d e t m o d e m d a i stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 75/147 5.3.11 memor y c haracteristics fla s h memor y th e char acte r i st ics a r e g i v en at t a = ? 40 t o 10 5 c unl ess ot he rwise specif ied . t a b l e 32 . f la sh memory c h a r ac ter i s ti c s symbol p a ra meter c onditions m in max u nit i dd supp ly cu rre n t rea d mo de f hc lk = 120 m h z with 3 w a it states , v dd = 3.3 v tbd m a wr ite / er ase mode s f hc lk = 120 m h z, v dd = 3 . 3 v tbd m a p o w e r-do w n mo de / ha lt, v dd = 3. 0 to 3 . 6 v tbd a t a b l e 33. f lash memor y pr ogramming sy mbol p a r a meter conditions min (1) ty p m a x (1) 1. guarante ed by design, not tested in production . unit t pr o g w o rd prog r a mm ing time t a = ?40 to +10 5 c 12 100 s t era se16 k b sector (16 kb) erase ti me 40 0 m s t era se64 k b sector (6 4 kb) erase ti me 70 0 m s t erase12 8 kb sector (1 28 kb) e r ase time 1 s t me mass er ase time tbd t bd ms v pr og prog r a mmin g v o ltage 3 2 -bit prog r a m op er a t io n 2 .7 3 . 6 v 1 6 -bit prog r a m op er a t io n 2 .1 3 . 6 v 8 - bit p r og r a m ope r a tion 1.8 3 .6 v t a b l e 34. f lash memor y pr ogramming with v pp symbol p a rameter co nd iti o n s min (1) ty p m a x (1) unit t pr o g doub le w o rd prog r a mming t a = 0 to + 4 0 c 76 0 s t erase16 k b s e ct or (16 kb) e r as e time t b d t erase64 k b s e ct or (6 4 kb) e r as e ti me t b d t erase1 28kb se cto r (1 28 kb) er a se ti me tbd t me ma ss erase ti me tbd v prog pro g ramming v o lta ge 2 .7 3.6 v v pp v pp v o l t a ge r a n g e 7 9 v i pp mi nim u m curren t sunk on the v pp pin 10 ma t vpp (2) cum u lativ e time dur ing which v pp is app lie d 1 h our electrical characteristics stm32f205xx, stm32f207xx 76/147 doc id 15818 rev 5 t a b l e 35 . f la sh memory en dura n ce a nd dat a ret e n t i o n 5.3.12 emc c haracteristics sus c eptibility tests ar e perf or med on a s a mple basis dur i ng de vice char acter i z a tion. fun ctional ems (elect r oma gn etic sus ceptibil i ty) while a simp le app licat ion is e x e c ut ed on t h e d e vice (t og gling 2 l e ds th ro ugh i / o po r t s). th e d e vice is str e ssed b y t w o e l ect r om agn et ic e v ent s u n t il a f a ilur e occurs . th e f a ilur e is ind i ca te d b y th e l e ds : el ec tr os t a t i c d i sc h a r g e (es d ) (p osit iv e an d n ega tiv e ) is ap plie d t o a ll de vice pins un t il a f u nctio nal distu r b a n c e occur s . this t e st is co mplia nt wit h t h e iec 6 100 0- 4- 2 st and ar d. ftb : a b u rs t of f a st tr an sie n t v o lt ag e ( p o sitiv e a n d ne ga tiv e ) is a p p lie d to v dd an d v ss t h ro ug h a 10 0 p f cap a cit o r , un til a f u n c t i o nal distu r b ance occur s . this t e st is com p lian t with t h e iec 610 00- 4- 4 sta nda rd . a de vice r e set a llo ws no r m a l o per at ion s t o be r e sume d. th e t e st r e sult s a r e g i v e n in ta b l e 3 6 . t h e y a r e b a sed on th e ems le v e ls a n d classes d e f i ned in app licat ion no t e an1 709 . 1. guarante ed by design, not tested in production . 2. v pp should only be connected du ring programmin g /erasing. symbol p a ra meter co nditions va l u e unit mi n (1 ) 1. based on characterizatio n , not tested in prod uction. ty p m a x n end en dur a n ce t a = ?40 to +85 c (6 suffi x v e rsi ons) t a = ?4 0 to + 105 c (7 su ffix v e rsio ns) 10 kcycles t ret da ta re ten t i on 1 kcy cle (2 ) at t a = 85 c 2. cycling perf ormed over t he whole temperature range. 30 y ears 1 kcy cle (2 ) at t a = 1 05 c 10 10 kcycles (2) at t a = 55 c 2 0 t a b le 36. e ms c h a r ac te ris t i c s sym b o l p a ram e ter c on di ti on s le ve l/ class v fesd v o ltage limi t s to be a ppl ied on an y i/o p i n to ind u ce a fun cti onal d i stu r bance v dd = 3.3 v , lqfp100 , t a = + 2 5 c , f hc lk = 75 mhz, conf or ms to iec 6 1 000-4 - 2 2b v eftb f a st tr a n sien t v o l t ag e b u rst l i mits to be app lied throu gh 100 p f on v dd and v ss pin s to indu ce a fun cti onal d istu r bance v dd = 3.3 v , l q fp100, t a = +25 c , f hc lk = 75 mhz, conf or ms to iec 6 1 000-4 - 2 4a stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 77/147 desi gning har d ene d software to a v oid nois e pr o b lems emc ch ar a cte r i za tio n an d opt imiza t io n ar e per f o r m ed at comp one nt le v e l with a t ypical a pplica t io n en vir o n m en t a nd simplif ied mcu sof t w a r e . it shou ld be n o t ed t h a t go od emc p e r f o r ma nce is h i ghly dep en den t o n th e user a p p lica t io n an d th e sof t w a re in par t i cular . th er ef or e it is re co mmen de d th at th e user a ppli e s emc sof t w a re opt imizat ion a n d p r e qua lifica t io n te st s in re lat i on wit h th e emc le v e l re que st ed f o r his app licat ion. sof t ware r eco mm e nda tions th e sof t w a r e flo w char t m u st includ e t he ma nag eme n t of r u na w a y cond itio ns su ch a s: co rr u p t e d pr og r a m co un te r une xpect ed res e t cr itical dat a cor r upt io n (con tr ol re gist er s . . . ) pre qua lific a tion t r ials mo st of th e commo n f a ilur e s (u ne xpe cte d re se t an d pr og r a m co un te r corr u p t i on ) can be reproduced b y man u ally f o rci ng a lo w state on the n r st pin or the oscillator pins f o r 1 second. t o com p let e t hese t r ials , esd st re ss ca n be ap plie d d i re ct ly o n th e de vice , o v er t he r a n g e of spe c if icat ion v a lu es . wh en un e xpe ct ed b eha vior is d e t e ct ed, t h e sof t w ar e can be ha rd ene d to p r e v en t un re co v e r a b l e er ro rs o ccu rr in g (s ee a p p lica t io n no te an 10 15 ) . elec tr oma g n e tic inte rf eren ce (emi) th e ele c t r oma gne tic f i eld em itt e d b y th e de vice ar e mo nit o r ed while a simp le ap plicat ion is e x ecuted (toggling 2 leds thro ugh the i/o por ts). this emissi on test is compliant w i th sae i e c619 67- 2 sta n d a rd wh ich sp ecifie s t h e t e st b o a r d a nd t he p i n load ing . 5.3.13 absolute maxim u m rati ngs (electrical sensitivity) ba se d on t h r e e d i f f e r e n t t e st s ( esd , lu) using sp ecific me asur eme n t m e t h o d s , th e de vice is str e s se d in o r de r to de te r m in e its pe r f or ma nce in te r m s of elect r ical se nsiti v it y . electr ostatic disc har g e (esd) ele c t r o sta tic dischar ge s ( a posit iv e th en a n ega t i v e p u lse sep a r a t e d b y 1 second ) ar e a pplie d t o th e pin s of each sam p le accor d in g to e a ch pin com b ina t ion. the sam p le siz e d epe nd s on t h e n u mb er o f supp ly p i ns in t h e de vice (3 p a r t s (n+1 ) supp ly pin s). t h is t e st con f o r ms to th e jesd22 -a11 4/ c101 st an dar d. t a b l e 37. emi c h ar act eri s ti cs symb ol p a r a me te r c on di ti on s monitored freq ue ncy ba nd ma x vs. [f hse /f hc l k ] unit 8/48 mhz 8 /7 2 mh z s emi p eak le v e l v dd = 3. 3 v , t a = 25 c , l q fp100 p a c kage co mp lia nt wi th iec619 67-2 0.1 to 30 mhz 9 9 dbv 30 to 130 mhz 2 6 1 3 130 mhz to 1ghz 2 5 31 sae em i le v e l 4 4 - electrical characteristics stm32f205xx, stm32f207xx 78/147 doc id 15818 rev 5 static latc h-up t w o comp leme nt ar y sta t i c t e sts ar e re quir e d o n six pa r t s to a sse ss th e lat ch- up pe rf or m an ce : a su pply o v e r v o lta g e is app lied t o ea ch po w e r supp ly pin a cu rr ent inje ct ion is ap plied t o e a ch inp u t , ou tp ut and co nf igur ab le i/ o p i n th ese t e sts ar e comp liant wit h ei a/jesd 7 8 a ic lat ch-u p sta nda rd . 5.3.14 i/o por t c h aracteristics general i nput/output c h aracteristic s unle ss ot he rwise sp ecif ied, th e pa r a m e t e rs giv e n in ta b l e 4 0 are der iv e d fr om t e st s p e r f o r me d und er t h e co ndit i on s sum m ar iz e d in ta b l e 1 0 . a ll i/os are cmos and ttl compliant. t a b l e 38. esd a b so lu te max i m u m rat i n g s symb ol ratin g s c on di tion s c lass maxim u m v a lu e (1 ) unit v esd(hbm) ele c trostatic discharg e v o ltage (hu m a n body mode l) t a = + 25 c c o nf or ming to jesd22-a114 2 200 0 v v es d ( cd m) ele c trostatic discharg e v o ltage (charg e de vice mo del) t a = + 25 c c o nf or ming to jesd22-c 101 ii 500 1. based on characterization results, no t teste d in p r oductio n. t able 39. elec tri c a l s e nsi t iv it i e s symbol p a ram e ter c onditions c lass l u st at ic l a t c h- up cl a s s t a = +1 05 c co nf o r m i n g to j esd 78 a i i l e v e l a t ab l e 40. i / o st at ic c h ara cte ri st ic s symb ol p a ram e ter c on di tio n s m i n t y p m a x un it v il i n p u t lo w le v e l v o lta g e tt l por t s 2.7 v v dd 3. 6 v v ss ?0 .3 0.8 v v ih st andard i/o input high le v e l v o lt age 2 v dd +0. 3 ft (1 ) i/o in put high l e v e l v o ltag e 2 5.5v v il i n p u t lo w le v e l v o lta g e cmos por ts 1.6 5 v v dd 3.6 v ? 0.3 0.3 v dd v ih stan dard i/o high l e v e l v o ltag e 0.7 v dd v dd +0 .3 ft (1 ) i/o in put high l e v e l v o ltag e cmos por ts 1.6 5 v v dd 3.6 v 5. 25 cmos por ts 2.0 v v dd 3. 6 v 5.5 v hy s stan dard io schmitt trigg e r v o ltage h ysteresis (2) 20 0 m v io ft schmitt tr ig ger v o ltag e h ysteresis (2) 5% v dd (3) mv stm 32f2 0 5 xx, stm32 f 20 7x x electrical characteristics doc id 15818 rev 5 79/147 all i / o s ar e cmos an d ttl com p lian t ( no sof t w ar e conf igu r at ion req u ir ed) , t h e i r cha r act e r i st ics co nside r t he mo st st r i ct cmo s - t echn olog y or ttl p a r a met e r s : fo r v ih : ?i f v dd is in th e [2 . 00 v - 3. 08 v] r ang e: cm os ch ar a c t e r i st ics b u t t t l includ ed ?i f v dd is in th e [3 . 08 v - 3. 60 v] r ang e: ttl cha r act e r i stics b u t cmos includ ed fo r v il : ?i f v dd is in th e [2 . 00 v - 2. 28 v] r ang e: ttl cha r act e r i stics b u t cmos includ ed ?i f v dd is in th e [2 . 28 v - 3. 60 v] r ang e: cm os ch ar a c t e r i st ics b u t t t l includ ed output drivi ng current th e gpi o s (g ene r a l pu r p ose inp u t / o u t p u t s) can sink or so urce u p to +/ -8 m a , an d sink +2 0 m a (w ith a re lax e d v ol ). i n t he u s e r ap plicat ion , t he n u mbe r of i / o pin s which can d r iv e cu rr ent m u st b e limit ed t o re sp ec t t h e a b s o lu te m a xi m u m r a ting spec ified in se ct i o n 5 . 2 : the su m of t h e cu rr ent s so urce d b y all t he i / o s o n v dd , p l us t h e maxim u m run consum pt ion of t h e mcu sour ced on v dd , can n o t e xce ed th e absolu t e ma xim u m r a t i ng i vd d (se e ta b l e 8 ). the su m of t h e cu rr ent s su nk b y a ll th e i/ os on v ss plu s th e ma xim u m ru n consum pt ion o f t he mcu su nk o n v ss c a n n o t e x ce ed th e a b s o lu te m a x i m u m r a tin g i vss (see ta b l e 8 ). output v o lta g e le vels unle ss ot he rwise sp ecif ied, th e pa r a m e t e rs giv e n in ta b l e 4 1 are der iv e d fr om t e st s p er f o r me d und er a m bie nt te mpe r at ur e an d v dd supp ly v o lt ag e cond itio ns su mma r iz ed in ta b l e 1 0 . all i / o s are cm os a n d t t l comp liant . i lk g stan dard i/o in pu t le akage curren t (4) v ss v in v dd 1 a f t i/o input leakage (4 ) v in = 5 v 3 r pu w eak pu ll-up equi v a le nt r e sistor (5 ) all pin s e xcept f o r p a 10 and pb12 v in = v ss 30 4 0 50 k p a 10 and pb12 8 1 1 15 r pd w eak pull - do wn equi v a le nt resi stor (5) all pin s e xcept f o r p a 10 and pb12 v in = v dd 30 4 0 50 k p a 10 and pb12 8 1 1 15 c io (6) i/o pi n ca pacitan ce 5 p f 1. ft = five -volt to lerant. 2. hysteresis volta ge between s c hmitt trigger switchin g levels. based on characte riza tion, not t ested in production. 3. wit h a minimum of 1 00 mv. 4. leakage could be higher than max. if n egativ e current is injected on adjacent pins. 5. pull-up and pull-down resistor s are designed w i th a true resistance in seri es with a switchable pmos/nmos. th is mos/nmos contribu tion to t he series resista n ce is mini mum (~10% order) . 6. guaran teed by design, no t teste d in p r oductio n . t a b l e 40. i / o st at ic c h ara c te ri st ic s (c ont in ue d) symb ol p a ram e ter c on di tio n s m i n t y p m a x un it electrical characteristics stm32f205xx, stm32f207xx 80/147 doc id 15818 rev 5 inp u t/output a c c h aracteristics th e de fin i tio n an d v a lue s o f inp u t / out pu t a c cha r act e r i st ics ar e giv e n in figu re 2 7 and ta b l e 4 2 , r e s p e ctiv e ly . unle ss ot he rwise sp ecif ied, th e pa r a m e t e rs giv e n in ta b l e 4 2 are der iv e d fr om t e st s p e r f o r me d und er t h e amb i ent te mpe r at ur e an d v dd supp ly v o l t a ge con d it ions su mma r i z e d in ta b l e 1 0 . t a b l e 41 . o utp u t v o lt a g e c h ara c t e ri st i c s (1) 1. pc13, pc1 4, pc15 and pi8 are supplied t hrough th e power sw itch. sin c e the switch only sinks a limited amount o f current (3 ma), the use o f gpios pc13 to pc15 and pi8 in output mode is limited: the speed should not exceed 2 mhz wit h a maximum load of 3 0 pf and these i/os must not be used as a current source (e.g . to drive an led). sy mbol p a rame ter c onditions m in ma x u nit v ol (2) 2. th e i io current sunk by the device must alw ays re spect the absolute maximu m rating specified in table 8 and the sum of i io (i/o p o rts and control pins) must not excee d i vss . output lo w le v e l v o ltage f o r an i/o pin w hen 8 pin s a r e su nk a t same time ttl po r t i io = +8 ma 2.7 v < v dd < 3. 6 v 0.4 v v oh (3) 3. th e i io current sourced by the device must always re spect the absolute maximum ra ting specif ied in ta ble 8 a nd the sum of i io (i/o port s and control pins) must not e x ceed i vdd . output hig h l e v e l v o l t ag e f o r an i/o p i n w hen 8 pins a r e so urced at sa me time v dd ?0.4 v ol (2 ) output lo w le v e l v o ltage f o r an i/o pin w hen 8 pin s a r e su nk a t same time cmos por t i io =+ 8ma 2.7 v < v dd < 3. 6 v 0.4 v v oh (3 ) output hig h l e v e l v o l t ag e f o r an i/o p i n w hen 8 pins a r e so urced at sa me time 2.4 v ol ( 2 )(4 ) 4. based on characterizatio n data, not te sted in production. output lo w le v e l v o ltage f o r an i/o pin w hen 8 pin s a r e su nk a t same time i io = +2 0 ma 2.7 v < v dd < 3. 6 v 1.3 v v oh (3)(4) output hig h l e v e l v o l t ag e f o r an i/o p i n w hen 8 pins a r e so urced at sa me time v dd ?1.3 v ol ( 2 )(4 ) output lo w le v e l v o ltage f o r an i/o pin w hen 8 pin s a r e su nk a t same time i io = +6 ma 2 v < v dd < 2.7 v 0.4 v v oh (3)(4) output hig h l e v e l v o l t ag e f o r an i/o p i n w hen 8 pins a r e so urced at sa me time v dd ?0.4 t a b l e 42. i / o a c c h ara c t e ri st i c s (1) ospeedry [1:0] bit va l u e (1 ) symbol p a rame te r c onditions m in t y p m ax unit 00 f ma x(io)o u t ma xi m u m freq uen cy (2) c l = 50 pf , v dd = 1.8 v to 3.6 v 2m h z t f(i o )ou t output hig h to lo w le v e l f a ll time c l = 50 pf , v dd = 1.8 v to 3.6 v tbd (3 ) ns t r(io)o u t output lo w to h i gh le v e l r i se time tbd (3 ) stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 81/147 01 f ma x(io)o u t ma xi m u m freq uen cy (2) c l = 50 pf , v dd < 2.7 v 2 5 t bd mhz c l = 10 pf , v dd > 2. 7 v 2 5 5 0 (4) mhz t f(i o )ou t output hig h to lo w le v e l f a ll time c l = 50 pf , v dd < 2. 7 v t bd (3 ) ns c l = 10 pf , v dd > 2. 7 v t bd (3 ) t r(io)o u t output lo w to h i gh le v e l r i se time c l = 50 pf , v dd < 2. 7 v t bd (3 ) c l = 10 pf , v dd > 2. 7 v t bd (3 ) 10 f ma x(io)o u t ma xi m u m freq uency (2) c l = 50 pf , 2 . 4 < v dd < 2. 7 v 5 0 (4) tbd m hz c l = 10 pf , v dd > 2. 7 v 5 0 (4) 100 (4 ) mhz t f(i o )ou t output hig h to lo w le v e l f a ll time c l = 50 pf , 2 . 4 < v dd < 2.7 v t bd (3 ) ns c l = 10 p f , v dd > 2.7 v t bd (3 ) t r(io)o u t output lo w to h i gh le v e l r i se time c l = 50 pf , 2 . 4 < v dd < 2.7 v t bd (3 ) c l = 10 p f , v dd > 2.7 v t bd (3 ) 11 f ma x(io)o u t ma xi m u m freq uency (2) c l = 20 pf , 2 . 4 < v dd < 2.7 v 1 00 (4 ) tbd m hz c l = 10 p f , v dd > 2.7 v 1 0 0 (4 ) 200 (4 ) mhz t f(i o )ou t output hig h to lo w le v e l f a ll time c l = 20 pf , 2 . 4 < v dd < 2 . 7 v t bd (3 ) ns c l = 10 p f , v dd > 2.7 v t bd (3 ) t r(io)o u t output lo w to h i gh le v e l r i se time c l = 20 pf , 2 . 4 < v dd < 2 . 7 v t bd (3 ) c l = 10 p f , v dd > 2.7 v t bd (3 ) -t exti p w pu lse wi dth of e xte r n a l sig nals de te ct ed b y t h e exti co ntro lle r 10 ns 1. th e i/o speed is configu r ed usin g the osp eedr y [ 1:0 ] bi ts. refe r to the st m32f2 0 /21xxx reference manual for a descri p ti on o f the gpiox_speedr gpio po rt output s peed regis t e r . 2. th e maximum frequency is defined in figure 2 7 . 3. guaran teed by design, no t teste d in p r oductio n . 4. fo r maximum frequencies ab ove 5 0 mhz, it is required t o use the co mpensa t ion cell. t a b l e 42. i / o a c c h ara c t e ri st i c s (1) ( c ont in ued) ospeedry [1:0] bit va l u e (1 ) symbol p a rame te r c onditions m in t y p m ax unit electrical characteristics stm32f205xx, stm32f207xx 82/147 doc id 15818 rev 5 figu re 27 . i/o a c c h ara c t e rist ics de finition 5.3.15 nrst pin c haracteristics th e nrst p i n inpu t d r iv e r use s cmos t e chno log y . i t is conn ecte d t o a per man e n t pu ll-u p resist or , r pu (s ee ta b l e 4 0 ). unle ss ot he rwise sp ecif ied, th e pa r a m e t e rs giv e n in ta b l e 4 3 are der iv e d fr om t e st s p e r f o r me d und er t h e amb i ent te mpe r at ur e an d v dd supp ly v o l t a ge con d it ions su mma r i z e d in ta b l e 1 0 . ai14131 10 % 90% 50% t r(i o )o u t output e x t e rna l o n 50p f m ax i m um f r e quenc y i s ac hi ev ed i f ( t r + t f ) 2/ 3 ) t and i f t he du t y c y c l e i s ( 45- 55% ) 10 % 50% 90% when loaded by 50pf t t r(io)out tab l e 43 . nrst pin c h ara c t e ri st ic s symb ol p a r a meter c on di tio n s m i n t y p m a x un it v il (nr s t ) (1) 1. guarante ed by design, not tested in production . nrst inp u t l o w l e v e l v o l t ag e ? 0.5 0 .8 v v ih (nr s t ) (1) nrst inp u t h i gh le v e l v o ltage 2 v dd +0 .5 v h ys(n r st) nrst sch m i t t tr i gge r v o l t a ge h ysteresis 200 mv r pu w e a k pu ll-up e quiv a len t resistor (2) 2. th e pull-up is design ed with a true resistance in seri es with a switcha b le pmos . this pmos contribution t o t h e seri es re s i s t ance must be min i mum (~10% order) . v in = v ss 30 4 0 50 k v f(nr st) (1 ) nrst inp u t filtere d pulse 10 0 n s v nf (nr s t ) (1 ) nrst inp u t n o t filtered p u lse v dd > 2 . 7 v 3 00 ns t nr st_ o ut gene r a ted reset pul se d u r a ti on int e r n al reset source 20 s stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 83/147 figu re 28 . r ec ommend ed nrst pin pro t e c tion 2. th e reset netwo rk protects t he device against par asitic resets. 3. th e user must ensure that the level on the n r st pin can go below the v il(nrst) max leve l specified in ta ble 4 3 . othe rwise the reset is not take n into account by the de vice. 5.3.16 tim time r c haracteristics th e pa r a me t e rs giv e n in ta b l e 4 4 and ta b l e 4 5 a r e g uar ant ee d b y de sig n . ref e r to sec t io n 5 .3 .1 4 : i/ o po r t ch ar a cte r i stic s f o r d e t a ils on t h e in pu t/ ou tp ut a l te r n at e f u n c t i on ch ar a c t e r i st ics (o ut pu t comp ar e , inp u t ca pt ur e , e xt e r n al cloc k, pwm out pu t ) . a i175 3 2 s tm 3 2f r pu nr s t (2) v dd filter intern a l re s et 0.1 f extern a l re s et circ u it (1) tab l e 44 . c h a rac t e r ist i c s of t i mx c onne ct ed to t h e apb1 domain (1) 1. timx is u s ed as a ge neral term to refer to the tim2, tim3, t i m4, t i m5, tim 6, t i m 7, and t i m1 2 t i mers. symbol p a ra meter c onditions min m ax unit t re s(tim) timer resolution tim e f timxclk = 60 mhz apb1= 30 m h z 1 t ti m xc l k 16.7 n s f ext timer e x ter n al cloc k frequ ency on ch1 to ch4 0 f timxclk /2 mhz 03 6 m h z re s ti m timer resolution 16 bit t cou nt e r 16 -b i t co un te r cl oc k p e r io d wh en in ter n a l cl oc k i s selected 1 65 536 t ti m xc l k 0 . 0 167 1 092 s 32 - b i t co un te r cl oc k p e r io d wh en in ter n a l cl oc k i s selected 1 t ti m xc l k 0 . 0 167 715 827 88 s t max_ co un t maxi m u m possib l e count 65 536 6 553 6 t ti m xc l k 71 . 6 s electrical characteristics stm32f205xx, stm32f207xx 84/147 doc id 15818 rev 5 t a b l e 45 . c h a rac t e r ist i c s of timx c onne ct ed to t h e apb2 domain (1) 1. timx is u s ed as a ge neral term to refer to the tim1, tim 8, t i m 9, t i m10, and t i m11 timers. symbo l p a rameter c on di tion s m in max u nit t re s(tim) timer resolution tim e f ti m xc l k = 120 mh z apb2 = 60 mhz 1 t ti m xc l k 8. 3 n s f ext timer e x ter n al cloc k frequ ency on ch1 to ch4 0 f ti mx c l k /2 mhz 03 0 m h z re s ti m timer resolution 16 bit t cou nt e r 16 -b i t co un te r cl oc k p e r io d wh en in ter n a l cl oc k i s selected 1 6 5536 t ti m xc l k 0 . 0083 546 s t max_ co un t maxi m u m possib l e count 655 36 655 36 t ti m xc l k 35 .7 9 s stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 85/147 5.3.17 comm unications interfaces i 2 c interface c h aracteristi cs unle ss ot he rwise sp ecif ied, th e pa r a m e t e rs giv e n in ta b l e 4 6 are der iv e d fr om t e st s p e r f o r me d und er t h e amb i ent te mpe r at ur e , f pclk1 fr eq uen cy an d v dd supp ly v o lt ag e conditions summar iz ed in ta b l e 1 0 . th e stm3 2f2 0 x a n d stm 32f 205 xx i 2 c int e r f a ce mee t s th e re qu irem ent s of t h e st an dar d i 2 c co mmun i ca tio n p r ot oco l w i th th e f o llo win g re str i ct ion s: th e i/o p i ns sd a a n d s c l ar e ma pp ed t o ar e no t ?t r u e ? o pen -d r a in . wh en co nf igur ed as op en- dr ain, t h e pmos con nect e d b e t w ee n t he i / o pin an d v dd is disab l ed, b u t i s still present. th e i 2 c char act e r i st ics are desc r i bed in ta b l e 4 6 . ref e r a l so to sec t io n 5 .3 .1 4 : i /o po r t char acter istic s f o r m o r e de ta ils on th e in pu t/o u t p u t alt e r n at e fun ct i on ch a r act e r i s t ics (sd a a nd scl) . t ab l e 46 . i 2 c c h ara c te ri st ic s symbol p a ra meter stan dar d mo de i 2 c (1) 1. guarante ed by design, not tested in production . f ast mode i 2 c ( 1 )(2 ) 2. f pclk1 must be hig her than 2 mhz to ach i eve the maximum st andard mo de i 2 c frequency. it must be higher th an 4 mhz to achie v e the maximum fast mode i 2 c frequ ency. unit mi n m ax m i n m a x t w(sc ll ) sc l cl oc k l o w ti me 4. 7 1 . 3 s t w( scl h ) scl cl oc k hi g h time 4. 0 0 . 6 t su(sd a ) sd a setup time 250 100 ns t h(sd a ) sd a data hold time 0 (3) 3. th e maximum hold time of the start co ndition has only to be met if the interface doe s not stretch t he low period of s c l signal. 0 (4 ) 4. th e device must inte rnally provide a hold time of at least 300ns for th e s d a signal in order to bridge the undefined regio n of the falling ed ge of scl. 90 0 (3) t r(s d a ) t r(sc l ) sd a an d sc l r ise ti me 10 00 2 0 + 0.1c b 30 0 t f(sd a) t f(s c l) sd a an d sc l f a ll time 300 3 00 t h ( st a) star t condition hold time 4. 0 0 . 6 s t su (st a ) re pea te d star t co ndi tio n setup time 4. 7 0. 6 t su(st o ) sto p co nd i tio n se tu p ti me 4. 0 0 . 6 s t w(st o: st a) stop to sta r t condi ti on ti me (b us free) 4. 7 1. 3 s c b ca paci t iv e l oad f o r each b u s li n e 400 4 00 pf electrical characteristics stm32f205xx, stm32f207xx 86/147 doc id 15818 rev 5 figu re 29 . i 2 c b us a c wa v e f orms a nd meas ure m ent c i r c u i t 1. measureme nt poin t s are done at cmos levels: 0.3v dd and 0 . 7v dd . t a b l e 47 . s cl fr eque nc y ( f pclk 1 = 3 0 mhz. ,v dd = 3.3 v) (1) ( 2) 1. r p = external pull-up re sista nce, f sc l = i 2 c speed, 2. fo r speeds around 200 khz, th e tole rance on the a c hieved sp eed is of 5 % . f o r other sp eed rang es, th e tolerance on th e ach i eved speed 2% . the s e variations depend on t he accuracy of the external components used to design the application. f scl (khz ) i2c_cc r v a lue r p = 4. 7 k 40 0 0 x8019 30 0 0 x8021 20 0 0 x8032 10 0 0 x009 6 50 0x0 12c 20 0x02 e e a i175 33 s t a rt s da 100 4.7k i2c bus 4.7k 100 v dd v dd s tm 3 2f s da s cl t f( s da) t r( s da) s cl t h( s ta) t w( s ckh) t w( s ckl) t su ( s da) t r( s ck) t f( s ck) t h( s da) s t a rt repe a ted s t a rt t su ( s ta) t su ( s to) s top t su ( s ta: s to) stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 87/147 i 2 s - spi interface c h aracterist i cs unle ss ot he rwise sp ecif ied, th e pa r a m e t e rs giv e n in ta b l e 4 8 f o r spi or in ta b l e 4 9 fo r i 2 s a r e d e r i v e d fr om t e st s p e r f o r me d un der th e am bien t t e m per a t ure , f pc lkx fr eq u e n cy an d v dd su pp ly v o lt ag e co nd itio ns su m m a r iz ed in ta b l e 1 0 . ref e r to se ct ion 5 .3 .1 4: i/o p o r t ch ar a cte r i st ics f o r m o r e d e ta ils o n t h e in pu t/ ou tp ut alt e r n at e fu nc tio n c h a r ac te r i stics ( n ss , sc k, m o si, m i so f o r spi a n d ws , c k , sd f o r i 2 s). t a b l e 48 . spi c h ara c t e ri st ic s (1) 1. remap ped spi1 ch aracterist ics to be determined. symbol p a ra meter c onditions m in max u nit f sck 1/ t c(sck) spi cl oc k freq uency maste r mode 30 mh z sl a v e mo de 30 t r(sck ) t f(sck) spi cl oc k r i se and f a ll time capacitiv e load: c = 30 pf 8 n s d u cy(sck) spi sl a v e in put cl oc k duty cycle sla v e mo de 3 0 7 0 % t su (nss) (2) 2. based on characterizatio n , not tested in prod uction. n s s setup time sla v e mod e 4 t pcl k ns t h ( nss) (2 ) ns s hold tim e sla v e mode 2 t pcl k t w(sckh) (2 ) t w(sckl) (2 ) sck h i gh a nd l o w ti me master mode , f pcl k = 36 mhz, presc = 4 50 60 t su (mi) (2 ) t su(si) (2 ) d a ta i npu t setup time master mode 5 sla v e mo de 5 t h (mi) (2 ) t h(si ) (2) d a ta i npu t hol d tim e master mode 5 sla v e mo de 4 t a(so ) (2 ) ( 3) 3. min time is for the minimum time to drive the outp u t and the max time is for the maximum time to valida te the dat a. data output access time sla v e mo de , f pc l k = 20 mh z 0 3 t pclk t di s(so) (2)(4) 4. min time is for the minimum time to invalidate the out put and the ma x time is for the maximu m time to put the dat a in h i -z d a ta o u tput disab l e time sla v e mo de 2 1 0 t v(so) (2)(1) d a ta o u tput v a lid time sla v e mod e (a fter ena b l e ed ge) 25 t v( mo) (2) ( 1 ) d a ta o u tput v a lid time maste r mode (a fter ena b l e ed ge) 5 t h(so ) (2 ) d a ta o u tput hold time sla v e mod e (a fter ena b l e ed ge) 15 t h (mo) (2 ) maste r mode (a fter enab le ed ge) 2 electrical characteristics stm32f205xx, stm32f207xx 88/147 doc id 15818 rev 5 figu re 30. spi timing d i a g ram - sla v e mod e and cpha = 0 figu re 31. spi timing d i a g ram - sla v e mod e and cpha = 1 (1) 1. measurement points are done at cmos levels: 0.3v dd and 0.7v dd . ai14134c sck input cp ha = 0 mo s i in p u t mi s o ou t p u t cp ha = 0 ms b o u t ms b i n bi t 6 o u t ls b i n ls b o u t cp o l =0 cp o l =1 bit1 in ns s input t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) ai14135 sck input cp ha = 1 mosi input mi s o ou t p u t cp ha = 1 ms b o u t msb in bi t 6 o u t ls b i n ls b o u t cp o l =0 cp o l =1 bit1 in t su(nss) t c(sck) t h(nss) t a(so) t w(sckh) t w(sckl) t v(so) t h(so) t r(sck) t f(sck) t dis(so) t su(si) t h(si) nss input stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 89/147 figu re 32. spi timing d i a g ram - master mo de (1) 1. measureme n t points are done a t cmos levels: 0.3v dd and 0.7v dd . ai14136 sck input cp ha = 0 mo s i outu t mi s o inp u t cp ha = 0 m s bin m s b out b i t 6 in l s b out l s b in cp o l =0 cp o l =1 b i t 1 out ns s input t c(sck) t w(sckh) t w(sckl) t r(sck) t f(sck) t h(mi) high sck input cp ha = 1 cp ha = 1 cp o l =0 cp o l =1 t su(mi) t v(mo) t h(mo) electrical characteristics stm32f205xx, stm32f207xx 90/147 doc id 15818 rev 5 t ab l e 49 . i 2 s c h ara c t e ri st ic s (1 ) 1. tbd = to be determined. s y mb ol p a rameter c o ndi tio n s m i n m a x u nit f ck 1/t c(ck) i 2 s clo c k freque ncy master tb d tbd mhz sla v e 0 tbd t r(ck) t f(c k ) i 2 s cloc k r i se and f a ll time capacitiv e load c l = 50 pf tbd ns t v(ws) (2) 2. based on desig n simulation and/or characte rization re sults, not tested in produ ction. ws v a lid time master tbd t h( ws) (2) ws hold time master tbd t su( w s) (2 ) ws setup time sla v e t bd t h( ws) (2) ws hold time sla v e t bd t w(c k h) (2 ) t w(c k l) (2 ) c k hi gh and l o w time master f pcl k = t b d , pres c = tbd tb d t su(sd _ mr ) (2) t su(sd _ sr ) (2) d a ta i npu t setup time master receiv er sla v e r e ceiv er tb d tbd t h(sd _mr ) (2)(3) t h(sd _sr ) (2) ( 3 ) 3. depen ds on f pclk . f o r example, if f pc lk =8 mhz, then t pclk = 1/f plcl k = 1 25 ns. d a ta i npu t hol d time master receiv er sla v e r e ceiv er tb d tbd t h(sd _mr ) (2) t h(sd _sr ) (2) d a ta i npu t hol d time master f pcl k = tbd sla v e f pcl k = tbd tb d tbd t v(sd_ s t) (2) ( 3 ) data output v a lid time sla v e transmitte r (after e nab l e edg e) tbd f pclk = tb d tbd t h(sd _st) (2) d a ta o u tput hold time sla v e transmitte r (after e nab l e edg e) tb d t v(sd_ m t) (2) ( 3 ) data output v a lid time master transmitte r (after e nab l e edg e) tbd f pclk = t b d tb d tbd t h(sd _mt) (2) d a ta o u tput hold time master transmitte r (after e nab l e edg e) tb d stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 91/147 figu re 33 . i 2 s sla ve t i ming dia g ra m ( p hilips p r ot oc ol) (1 ) 1. measureme nt poin t s are done at cmos levels: 0.3 v dd and 0 . 7 v dd . 2. lsb tran smit/receive o f the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. figu re 34 . i 2 s mast er t i ming dia g r a m (philips p r ot oc ol) (1) 1. based on characterizatio n , not tested in prod uction. 2. lsb tran smit/receive o f the previ ously transmitted byte. no lsb transmi t/receive is sent before the first byte. ck inp u t c p ol = 0 c p ol = 1 t c(ck) w s inp u t s d tr a n s mit s d receive t w(ckh) t w(ckl) t su (w s ) t v( s d_ s t) t h( s d_ s t) t h(w s ) t su ( s d_ s r) t h( s d_ s r) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 1 b l s b receive (2) l s b tr a n s mit (2) ck o u tp u t c p ol = 0 c p ol = 1 t c(ck) w s o u tp u t s d receive s d tr a n s mit t w(ckh) t w(ckl) t su ( s d_mr) t v( s d_mt) t h( s d_mt) t h(w s ) t h( s d_mr) m s b receive bitn receive l s b receive m s b tr a n s mit bitn tr a n s mit l s b tr a n s mit a i14 88 4 b t f(ck) t r(ck) t v(w s ) l s b receive (2) l s b tr a n s mit (2) electrical characteristics stm32f205xx, stm32f207xx 92/147 doc id 15818 rev 5 usb o t g f s c h aracteristics the usb o t g interf ac e is u sb-if cer t ified (full-spee d). th is int e rf ace is p r e s e n t i n bot h th e usb o t g hs a n d usb o t g fs co nt ro ller s . t a b l e 50 . u sb o t g fs sta r tup t i me symbol p a r a mete r max unit t st ar tup (1) 1. guarante ed by design, not tested in production . us b o t g fs tr ansceiv er star tup time 1 s t a b l e 51 . u sb o t g fs dc el ect ri ca l c h a r ac te ris t i c s symbol p a rame ter c onditions m in. (1) 1. all the voltages are mea s ured from t he local groun d potential. ty p . m a x . (1) unit in pu t le vels v dd usb o t g f s oper a ting vo l t a g e 3. 0 (2 ) 2. th e stm32f 20x a nd stm32f 205xx u s b otg f s funct i onality is ensured down to 2.7 v but no t the full usb otg fs electrical c haracteristics which are degraded in the 2.7-to-3.0 v v dd voltage rang e. 3.6 v v di (3) 3. guarante ed by design, not tested in production . diff e ren t i a l inp u t sen siti vity i(usb_fs_dp/dm , usb_hs_dp/d m ) 0.2 v v cm (3) diff e ren t i a l common mode ra n g e includ es v di rang e 0 .8 2.5 v se (3) sing le end ed receiv er th reshol d 1.3 2 .0 ou tpu t le vels v ol sta t i c ou tp ut le v e l lo w r l of 1 . 5 k to 3. 6 v (4) 4. r l is the load connected on the u s b ot g f s drivers 0.3 v v oh sta t i c ou tp ut le v e l high r l of 1 5 k to v ss (4) 2.8 3 .6 r pd p a 11, p a 1 2 , pb14 , pb15 (usb_fs_dp/dm , usb_hs_d p/dm) v in = v dd 1 7 21 24 k p a 9, pb13 (o tg_fs_vb us , ot g _ h s _ v b u s ) 0.65 1.1 2 .0 r pu p a 1 2 , p b 15 ( u sb _f s_ dp , usb_hs_dp ) v in = v ss 1.5 1 .8 2.1 p a 9, pb13 (o tg_fs_vb us , ot g _ h s _ v b u s ) v in = v ss 0 . 2 5 0. 37 0. 5 5 stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 93/147 figu re 35 . u sb o t g fs timin g s: d e f i nit i o n o f dat a si gn al r i s e and f a l l t i me ai14137 t f d i ffe r e n ti a l da t a li n e s v ss v cr s t r crossover points electrical characteristics stm32f205xx, stm32f207xx 94/147 doc id 15818 rev 5 usb hs c h aracteristic s t a b l e 52 . u sb o t g fs electr i ca l c h a r acte r istic s (1 ) 1. guarante ed by design, not tested in production . drive r c h ar acter istics symb ol p ar amete r c on di tio n s m in max u n i t t r ri se time (2) 2. measured from 10% to 90% of the data signal. for more de tailed informations, please refer to usb specification - chapt er 7 (version 2.0). c l = 50 pf 42 0 n s t f fa l l t i m e (2 ) c l = 50 pf 4 2 0 n s t rfm ri se / f a l l time mat chin g t r /t f 9 0 110 % v cr s output si gnal crosso v e r v o ltage 1.3 2 .0 v t a b l e 53. c loc k timing parameter s pa r a m e t e r (1 ) 1. guarante ed by design, not tested in production . symb ol min n omin al max u ni t f r e que ncy (first tr an sition) 8-bi t 1 0% f st ar t_8b i t 5 4 60 66 m h z f r e que ncy (stead y state) 500 p p m f stead y 59 .97 6 0 6 0.03 mh z duty cycle (first tr ansition) 8-bit 10% d st ar t_8 b it 4 0 50 60 % duty cycle (steady state) 500 ppm d stead y 4 9 .975 5 0 50.025 % ti me to re ach th e stea dy state freq uency and duty cycle a f ter th e fi rst transitio n t stead y 1.4 m s cloc k st ar t u p time after the de-a s se r t io n of susp endm p e r i ph er a l t st ar t_dev 5.6 ms host t st ar t_ho st phy prep ar a t io n time a f ter the first transi t io n of the in put cloc k t prep s jitter t jitter ps rise time fa l l t i m e t rise t fa l l ns stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 95/147 figu re 36 . u lpi timin g d i a g ram etherne t c h aracteristic s ta b l e 5 5 sho w s the et he r n e t o per a t ing v o lt ag e . ta b l e 5 6 giv e s t h e list o f et he r n e t ma c sig nals f o r t h e smi (st a t i on ma na gem ent int e r f a ce) a nd fig u r e 37 sho w s t h e cor r e spon din g tim i ng dia g r a m . t a b l e 54 . u lpi ti min g p a rame te r s y m bol va l u e (1 ) 1. v dd = 3 v to 3.6 v and t a = ?40 to 8 5 c. unit min. max. ou tp ut clo c k setup time ( contr ol in) t sc , t sd 6.0 n s hold time (control in) t hc , t hd 0.0 n s ou tp ut d ela y (con tro l o ut ) t dc , t dd 9.0 n s in put cl oc k (option a l) setup time ( contr ol in) t sc , t sd 3.0 n s hold time (control in) t hc , t hd 1.5 n s ou tp ut d ela y (con tro l o ut ) t dc , t dd 6.0 n s t a b l e 55 . e t h er net dc e l ect ri ca l c h a r act er is ti cs sy mbol p a r a mete r m in. (1) 1. all the voltages are mea s ured from t he local groun d potential. max. (1 ) unit in pu t l e vel v dd ether net o p e r ating v o ltage 3.0 3 .6 v # l o c k # o n t r o l ) n s t p d a t a ) n b i t # o n t r o l o u t d i r n x t d a t a o u t b i t d a t a o u t b i t t $ $ $ t $ $ $ t $ $ t $ # t $ # t ( $ t 3 $ t ( # t 3 # a i b electrical characteristics stm32f205xx, stm32f207xx 96/147 doc id 15818 rev 5 figu re 37 . e t h er net smi timing dia g ra m ta b l e 5 7 g i v e s th e list of eth e r n et m a c s i gn a l s f o r th e rm ii an d fig u r e 38 sho w s the co rr es po nd in g tim i ng d i ag r a m. figu re 38 . e t h er net rmii t i ming d i a g ram t a b l e 56 . d yn ami cs c h a r ac te ris t i c s : eth e rne t ma c s i gn al s f o r smi (1) 1. tbd stand s for to be dete r mined. symbol rating min t yp max u nit t mdc mdc c ycle time (1.71 m hz, ahb = 72 mhz) tb d t bd t b d n s t d(md io) mdio wr ite data v a l id ti me tbd t bd tbd n s t su(md io) rea d data setu p ti me tbd t bd tbd n s t h(md io) rea d data hold time tbd t bd tbd n s t ab l e 57 . d yn ami cs c h a r ac te ris t i cs : eth erne t ma c s i gn al s f o r rm ii (1) 1. tbd stand s for to be dete r mined. symb ol rating m i n t yp max u n i t t su(r xd ) rece iv e da ta setup time tbd t bd tbd n s t ih ( r xd ) rece iv e da ta ho ld ti me tbd t bd tbd n s t su ( crs) carr i e r se nse set-up ti me tbd t bd tbd n s t ih ( cr s ) carr i e r se nse hol d time tbd t bd tbd n s t d ( txen) t r ansmit ena b l e v a l i d del a y time 0 9 .6 21.9 n s t d( tx d ) t r ansmit data v a l i d del a y time 0 9 .9 2 1 n s eth_mdc eth_mdio(o) eth_mdio(i) t mdc t d(mdio) t su (mdio) t h(mdio) a i15666c rmii_ref_clk rmii_tx_en rmii_txd[1:0] rmii_rxd[1:0] rmii_crs_dv t d(txen) t d(txd) t su(rxd) t su(crs) t ih(rxd) t ih(crs) ai15667 stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 97/147 ta b l e 5 8 g i v e s th e list of eth e r n et m a c s i gn a l s f o r m ii an d fi gur e 3 8 sho w s the co rr es po nd in g tim i ng d i ag r a m. figu re 39 . e t h er net m i i timin g dia g ram can (contr o ller area netw ork) inter f ace ref e r to se ct ion 5 .3 .1 4: i/o p o r t ch ar a cte r i st ics f o r m o r e d e ta ils o n t h e in pu t/ ou tp ut alt e r n at e fu nc tio n c h a r ac te r i stics ( c antx a n d canrx ). t a b l e 58 . d yn ami cs c h a r ac te ris t i c s : eth e rne t ma c s i gn al s f o r mi i (1) 1. tbd stand s for to be dete r mined. symbol rating min t yp max u nit t su (rxd ) r e ceiv e d a t a se tu p time t b d t bd tbd n s t ih(r xd ) re ce i v e da ta ho l d ti me tb d tbd t b d n s t su(d v) d a ta v a lid set u p t ime t b d t bd tbd n s t ih (d v) d a ta v a lid h o ld time tbd t bd tbd n s t su( e r) error setup time tb d t bd tbd n s t ih ( e r) error hold tim e tb d t bd tbd n s t d(txen) t r a n smit en ab l e v a lid d e la y time 13 .4 1 5 .5 17.7 n s t d(txd ) t r a n smit da ta v a lid de la y time 12 .9 1 6 .1 19.4 n s mii_rx_clk mii_rxd[3:0] mii_rx_d v mii_rx_er t d(txen) t d(txd) t su(rxd) t su(er) t su(d v) t ih(rxd) t ih(er) t ih(d v) ai15668 mii_tx_clk mii_tx_en mii_txd[3:0] electrical characteristics stm32f205xx, stm32f207xx 98/147 doc id 15818 rev 5 5.3.18 12-bit adc c haracteristics unle ss ot he rwise sp ecif ied, th e pa r a m e t e rs giv e n in ta b l e 5 9 are der iv e d fr om t e st s p e r f o r me d und er t h e amb i ent te mpe r at ur e , f pclk2 fr eq uen cy an d v dd a supply v o ltage conditions summar iz ed in ta b l e 1 0 . t a b l e 59. adc c h a r ac te ri sti c s symb ol p a ram e ter co nd i t i o ns mi n t yp max u nit v dd a p o w e r supply 1.8 3 .6 v v ref+ p o sitiv e ref e rence v o lta g e 1 .6 5 v dd a v i vref cu rrent o n th e v ref inpu t pi n 160 (1 ) 220 (1 ) a f adc adc clo c k freque ncy v dd a = 1.8 to 2.4 v 0.6 1 5 m hz v dd a = 2.4 to 3.6 v 0.6 3 0 m hz f trig (1) exter nal tr ig ger freq uen cy f adc = 30 mhz 8 23 khz 17 1 / f adc v ain co n v e r si on v o ltag e r a n g e (2) 0 (v ssa or v ref- tied to g r ound) v re f+ v r ain (1) exter nal in put impeda nce see eq uation 1 fo r de tai l s 50 k r adc (1 ) sam p ling s witch resistance 1 k c adc (1 ) inter nal samp le and h o ld ca pacitor 8p f t la t (1) inj e cti on tr igge r con v ersion l a tency f adc = 30 mhz 0 .1 00 s 3 (3) 1/ f adc t la tr (1) re gul ar tr ig ger co n v ersio n l a tency f adc = 30 mhz 0 .0 67 s 2 (3) 1/ f adc t s (1) s a mpling t i me f adc = 30 mhz 0 .10 0 16 s 3 4 80 1/ f adc t st ab (1) p o w e r-up ti me 0 0 1 s t con v (1) t o tal con v ersion time (inclu ding sa mp ling time) f adc = 30 mhz 12-bi t resol uti on 0.5 16.40 s f adc = 30 mhz 10-bi t resol uti on 0 . 4 3 16.34 s f adc = 30 mhz 8- bi t re sol u ti o n 0 . 3 7 16.27 s f adc = 30 mhz 6- bi t re sol u ti o n 0.3 16.20 s 9 to 492 (t s f o r sampling +n-bit r e so lution f o r succ essiv e ap pro x i m a t i on) 1/ f adc stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 99/147 equation 1: r ai n max f o rm ula th e fo rmu l a abo ve ( equatio n 1 ) is used to determin e th e ma ximum e xte rn al impe dan ce allo wed for an error belo w 1/4 o f lsb. h e re n = 12 (from 12-bit resolution) . a note: adc a c cur a cy vs . n e g a t i v e inject ion cur r e n t : i n je ct in g a neg at iv e curr en t o n an y o f t he st and ar d (n on- ro b u st) ana log in put pin s shou ld be a v oid ed as t h is sign if ica n t l y r edu ces t h e a c cur a cy of t he con v er sio n be ing pe rf or med o n an ot her ana log in put . it is r e comme n d ed t o f s (1) s a mp ling rat e (f adc = 30 mhz) 12-bi t resol uti on single adc 2 m sps 12-bi t resol uti on inter l e a v e du al adc mode 4 m sps 12-bi t resol uti on in te r l ea v e t r ipl e adc mode 6 m sps i vref+ adc v ref dc cu rren t co nsumption in co n v ersio n mo d e f adc = 30 mhz 3 sampli ng time 12-bi t resol uti on tbd a f adc = 30 mhz 480 sampl i ng time 12-bi t resol uti on tbd a i dd a adc vdd a dc current co nsumption in co n v ersio n mo d e f adc = 30 mhz 3 sampli ng time 12-bi t resol uti on tbd a f adc = 30 mhz 480 sampl i ng time 12-bi t resol uti on tbd a 1. based on characterization, not tested in prod uction. 2. v ref+ is internally connected to v dda and v ref- is internally connected to v ssa . 3. fo r external triggers, a dela y of 1/ f pclk2 must be add ed to the latency specified in t able 5 9 . t a b l e 59. adc c h a r ac te ri sti c s ( c on ti n u ed ) symb ol p a ram e ter co nd i t i o ns mi n t yp max u nit table 60. adc accuracy (1) 1. better performance could be a c hieved in restricted v dd , frequency and temperature ranges. sy mbol p a ra meter t est conditions t yp ma x (2) 2. based on characterizatio n , not tested in prod uction. unit et t otal un adju ste d e r ro r f pcl k 2 = 60 mhz, f adc = 30 mhz, r ai n < 10 k , v dd a = 1. 8 v t o 3. 6 v 2 5 lsb eo off set error 1.5 2.5 eg gain err o r 1.5 3 ed di ff erential li nea r i ty e r ro r 1 2 el integ r al linear i ty error 1.5 3 electrical characteristics stm32f205xx, stm32f207xx 100/147 doc id 15818 rev 5 a dd a schot t k y dio d e ( p in t o g r oun d) t o sta n d a r d ana log p i ns which m a y p o t ent ia lly inje ct n ega tiv e cu rr ent s . an y positiv e injectio n cu rr en t w i th in th e limits specified f o r i inj(pin) a nd i inj(pin) in section 5 .3.14 do es not af f e ct t he adc accur a cy . figure 40. adc accura c y c h aracteristics figu re 41 . t ypica l co nnec t ion dia g ra m u s ing th e adc 1. refer to ta b l e 5 9 for the va lues of r ai n , r adc an d c adc . 2. c pa ras i tic rep r esents the capacitance of the pc b (depende nt on solde r in g and pcb layo ut quality) plus the pad capacit ance (roug hly 7 pf ) . a high c p a ra sitic valu e downgrades conversion ac curacy. t o remed y this, f adc should be redu ced. e o e g 1l s b id e a l (1 ) e x am pl e of an actu al tr an sfe r cur ve (2 ) the id ea l tr an sf er cu rve ( 3) e nd po in t co rr el a t i on li n e e t = t ota l u n a d j u sted er ro r: ma ximu m d e via tion be t w ee n t h e a ctu a l an d t h e id ea l tr an sf er cu rve s. e o = off set e r r o r : d e vi ati o n be tw ee n th e fi r st actu al tr a n siti on an d t he fi rst id e a l on e. e g =g ai n er ror : d e via t io n be t w ee n t h e last id ea l tr a n sition an d t he la st a ctua l on e. e d = diffe re ntia l lin e a ri ty e rro r: m a xim um d e via tion be t w ee n a ct u a l st ep s an d t h e id ea l on e. e l = i n t eg ra l li ne ar ity e rr o r: ma ximu m d e via t ion b e twe en an y a ctua l t r a n sition a n d th e en d po in t cor r e l at io n li ne. 4095 4094 4093 5 4 3 2 1 0 7 6 1 23 456 7 4093 4094 4095 4096 (1 ) (2 ) e t e d e l (3) v dd a v ss a ai14395b v ref+ 4096 (or depending on pac kage)] v dd a 4096 [1lsb ideal = a i175 3 4 s tm 3 2f v dd ainx i l 1 a 0 . 6 v v t r ai n (1) c p a r as itic v ain 0. 6 v v t r adc (1) c adc (1) 12- b it con v er ter sa mple a nd hold adc con v er ter stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 101/147 general pcb desi gn guide lines p o w e r sup p ly decou plin g sh ou ld be pe rf or med a s sho w n in fig u r e 42 or figu re 4 3 , d epe nd ing on wh et her v ref+ is co nn e cte d to v dd a or n o t . th e 10 n f ca pacit or s sho u ld be cer a mic (go o d q ualit y). the y sh ould b e pla c e d t hem a s close as possib l e to t h e ch ip . figu re 42 . p o w er s uppl y and re f e re nce d eco uplin g (v ref + not connecte d to v dd a ) 1. v ref+ and v re f ? inputs are available only on 100-p i n packages. figu re 43 . p o w er s uppl y and re f e re nce d eco uplin g (v re f+ connected to v dd a ) 1. v ref+ and v re f ? inputs are available only on 100-p i n packages. v ref+ s tm 3 2f v dda v ss a /v ref- 1 f // 10 nf 1 f // 10 nf a i175 3 5 ( s ee note 1) ( s ee note 1) v ref+ /v dda s tm 3 2f 1 f // 10 nf v ref? /v ss a a i175 3 6 ( s ee note 1) ( s ee note 1) electrical characteristics stm32f205xx, stm32f207xx 102/147 doc id 15818 rev 5 5.3.19 d a c elect rical specifications t a b l e 61. d a c c h ara c t e ri st ic s symbol p a ra meter m in t y p m ax unit comments v dd a an alog su pply v o l t a g e 1 .8 3.6 v v re f+ r e f e ren ce su ppl y v o lta g e 1 .8 3.6 v v ref+ v dd a v ssa groun d 0 0 v r lo a d (1) r e sistiv e loa d with b u ff er on 5 k r o (1) imped ance ou tp ut wi th b uff er of f 15 k w hen t h e b u ff er i s o f f , th e mi nim u m resistiv e l oad be tw een d a c_ out a nd v ss to h a v e a 1% accur a c y is 1.5 m c lo ad (1) c apaci t iv e load 5 0 pf ma xi m u m capaci t i v e load a t d a c_ out p i n (when the b u ff er i s on). da c _ o u t min (1) l o w e r d a c_out v o lta ge w i th b u f f er on 0. 2 v it g i v e s the maxim u m ou tp ut e xcursio n of the d a c . it co rre spond s to 12-b i t in put co de (0x0e0) to (0xf1c) at v ref+ = 3. 6 v a n d (0x 1 c 7 ) t o (0 xe38 ) at v ref+ = 1. 8 v da c _ o u t ma x (1) h i ghe r d a c_out v o lta ge w i th b u f f er on v dd a ? 0.2 v da c _ o u t min (1) l o w e r d a c_out v o lta ge w i th b u f f er of f 0. 5 m v it g i v e s the maxim u m ou tp ut e xcursio n of the d a c . da c _ o u t max (1) h i ghe r d a c_out v o lta ge w i th b u f f er of f v ref+ ? 1lsb v i vref+ d a c dc v ref current co nsumption in q u ie sce n t mod e (stan d b y mode) 220 a with no load, w o rst code (0xf 1c) at v ref+ = 3. 6 v in ter m s of dc co nsumption o n the inpu ts i dd a d a c dc vdd a cu rre n t co nsumption in q u ie sce n t mod e (stan d b y mode) 380 a w i th no loa d , mid d le cod e (0 x800) o n th e inpu ts 480 a with no load, w o rst code (0xf 1c) at v ref+ = 3. 6 v in ter m s of dc co nsumption o n the inpu ts dnl (2 ) d iff erentia l n on lin ear i t y d i ff erence be tw ee n tw o co nsecutiv e cod e -1lsb) 0 .5 lsb giv e n f o r th e d a c in 10 -bit co nfiguration . 2 l s b giv e n f o r th e d a c in 12 -bit co nfiguration. inl (2) integ r a l non li near ity (d iff e rence b e t w e e n mea sured v a l ue at code i a nd the v a lu e at co de i on a l i ne dra w n be tw ee n code 0 a nd last code 1 023) 1 l s b giv e n f o r th e d a c in 10 -bit co nfiguration. 4 l s b giv e n f o r th e d a c in 12 -bit co nfiguration. stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 103/147 figu re 44 . 1 2- bit b u f f e r ed /non- b u ff e r ed d a c 1. th e dac integra t es an output buffer that can be used to r educe the outp u t impe dance and to dr ive external loads directly without the use o f an external operation al amplifier. the buffer can be b y passed by conf iguring t he bof f x bit in th e dac_c r reg i ster. of fset (2 ) off set error (d iff e rence be tw ee n mea sured v a l ue at code (0 x8 00) and the i deal v a lue = v ref+ /2 ) 10 m v giv e n f o r th e d a c in 12 -bit co nfiguration 3 l s b giv e n f o r th e d a c in 10 -bit a t v ref+ = 3. 6 v 12 l sb giv e n f o r th e d a c in 12 -bit a t v ref+ = 3. 6 v gain error (2) gai n err o r 0. 5 % giv e n f o r th e d a c in 12 bit co nfiguration t settling (2 ) se tt lin g ti me (f ull scal e : f o r a 1 0 -bit inp u t cod e transition b e tw e en th e lo w e st an d the h ighest in put co des when d a c_out rea ches fi nal v a l u e 4 lsb 34 s c lo a d 50 pf , r lo a d 5 k thd (2 ) t o tal har m oni c di sto r tio n bu ff e r o n db c lo a d 50 pf , r lo a d 5 k up date rate (1 ) max freque ncy f o r a corre ct d a c_out cha nge wh en smal l v a r i a t i on in the inp u t co de (from code i to i+ 1lsb) 1m s / s c lo a d 50 pf , r lo a d 5 k t w akeup (2 ) w a k e up t i me from of f s t ate (setting the enx bit in th e d a c co nt ro l re gi st er) 6. 5 10 s c lo a d 50 pf , r lo a d 5 k i npu t code b e tw ee n lo w e st an d h i gh est po ssi b le on es . psrr+ (1) p o w e r su pply reje ctio n r a tio (to v dd a ) (static dc mea surement) ?67 ?40 db n o r lo a d , c lo ad = 50 p f 1. guaran teed by design, no t teste d in p r oductio n . 2. guaran teed by characterizati on, no t teste d in p r oductio n . t a b l e 61. d a c c h ara c t e ri st ic s (c ont in u e d) symbol p a ra meter m in t y p m ax unit comments r load c load b u ffered/non- bu ffer ed d a c d a cx_out b u ff er(1) 12 - b it digit a l t o a n a log con v er ter a i17157 electrical characteristics stm32f205xx, stm32f207xx 104/147 doc id 15818 rev 5 5.3.20 t e mperature sen sor c h aracteristics 5.3.21 v ba t monitoring c haracteristics 5.3.22 embed ded ref e rence v o lta g e th e pa r a me t e rs giv e n in ta b l e 6 4 a r e de r i v e d f r o m te sts p e r f o r m e d un de r am b i en t t e m per a t ure and v dd su pply v o lt ag e co ndit i o n s sum m ar iz ed in ta b l e 1 0 . t a b l e 62 . t s c h a r ac te ri sti c s sy mbol p a ram e ter m in t y p m ax unit t l (1 ) 1. based on characterizatio n , not tested in prod uction. v sense line a r i ty with temp er a t ure 1 2 c av g _ s l o p e (1 ) a v erage slo pe 2 .5 mv/c v 25 (1) v o ltag e at 25 c 0.76 v t st ar t (2 ) 2. guarante ed by design, not tested in production . star tu p time 4 1 0 s t s_ t e mp (3 )(2) 3. shorte st sampling time can be d etermined in the application by multiple iterations. adc sampli ng ti me w hen rea d ing the temperature 1c accur a cy 16 s t a b l e 63 . v ba t moni t o ri ng c h ar act er is ti cs sy mbol p a ram e ter m in t y p m ax unit r (1 ) resi stor br i dge f o r v ba t tbd k o h m q (1) r a ti o on v ba t me asuremen t 2 er (1 ) 1. guaranteed by design, not tested in production. error on q - 1 + 1 % t s_vba t (2 ) ( 2) 2. shorte st sampling time can be d etermined in the application by multiple iterations. adc sampli ng ti me w hen rea d ing the v ba t 1mv accur a cy tbd s t a b l e 64 . e mb ed ded i n t e rn al r e f e renc e v o l t a g e symbol p a ram e ter c onditions min ty p max u nit v ref i nt inter nal ref e rence v o lta g e ? 40 c < t a < +10 5 c 1.16 1.20 1.26 v ? 40 c < t a < +85 c 1.16 1.20 1.24 v t s_vrefin t (1) adc sampl i ng time when rea d in g the i n ter n al ref e re nce v o ltage 5.1 tbd (2) s stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 105/147 5.3.23 fsmc c haracteristics asyn c h r onou s wa v e f o rms and timings fig u r e 45 t h r o u gh fig u r e 48 r epr esen t a s ynchr o n o u s w a v e f o r m s a nd ta b l e 6 5 t hro ug h ta b l e 6 8 pr o v id e th e co rr espo ndin g tim i ngs . th e r e sult s sho w n in t hese t a b l es a r e o b t a ine d wit h th e f o llo wing fsmc conf igu r at ion : add r essset up time = 0 add r essholdt ime = 1 da ta se tu ptim e = 1 figu re 45 . a sy nc hr onou s non- m u lt ip le x e d sram/psram/nor r ead wa vef or ms 1. mode 2/b, c and d on ly. in mode 1, fsmc_nad v is not used. v r e ri nt (2) inter nal ref e rence v o lta ge spre ad o v er the te mp er a t u r e rang e v dd = 3 v 10 mv 10 mv t c oef f (2) t e mpe r ature coefficien t 100 pp m/c 1. shorte st sampling time can be d etermined in the application by multiple iterations. 2. guarante ed by design, not tested in production . t a b l e 64 . e mb ed ded i n t e rn al r e f e renc e v o l t a g e symbol p a ram e ter c onditions min ty p max u nit data fsmc_ne fsmc_nbl[1:0] fsmc_d[15:0] t v(bl_ne) t h(data_ne) fsmc_noe address fsmc_a[25:0] t v(a_ne) fsmc_nwe t su(data_ne) t w(ne) ai14991b w(noe) t t v(noe_ne) t h(ne_noe) t h(data_noe) t h(a_noe) t h(bl_noe) t su(data_noe) fsmc_nadv (1) t v(nadv_ne) t w(nadv) electrical characteristics stm32f205xx, stm32f207xx 106/147 doc id 15818 rev 5 figu re 46 . a sy nc hr onou s non- m u lt ip le x e d sram/psram/nor write wa vef or ms 1. mode 2/b, c and d on ly. in mode 1, fsmc_nad v is not used. t a b l e 65 . a sy nc hr onou s non- m u lt ip le x e d sram/psram/nor r ead t i m i ng s (1 ) (2) 1. c l = 15 pf . 2. based on characterizatio n , not tested in prod uction. sym b ol p a ra meter m in max u nit t w(n e ) fsmc_ n e lo w time 5t hc lk ? 1.5 5 t hc lk + 2 n s t v(no e_ ne) f s mc_nex lo w to f s mc_no e lo w 0 .5 1. 5 n s t w(n o e) fsmc_ n oe lo w time 5t hc lk ? 1.5 5 t hc lk + 1. 5 n s t h(n e _n oe ) f s mc _n o e h i gh t o fsm c _n e hi g h ho l d ti me ? 1 . 5 n s t v(a_n e ) f s mc_nex lo w to f s mc_a v a lid 7 ns t h(a_ noe) addre s s ho ld ti me a f ter fsmc_n oe high 0.1 n s t v(bl_ n e) fsmc_ n ex lo w to fsmc_bl v a lid 0 n s t h(bl _n oe) fsmc_ b l h o ld time afte r fsmc _noe hi gh 0 n s t su(d at a_ ne) data to fsmc_nex hig h se tu p time 2t hc lk + 25 ns t su(d at a_ no e) data to fsmc_noex high setup time 2t hc lk + 25 ns t h ( da ta _n oe) data hol d ti me a f ter fsmc_noe high 0 n s t h(d a t a _ n e) data hol d ti me a f ter fsmc_nex hig h 0 n s t v(nad v _ n e) fsmc_nex lo w to fsmc_nad v lo w 5 ns t w(n a d v ) fsmc_nad v lo w time t hc lk + 1. 5 n s nbl data fsmc_nex fsmc_nbl[1:0] fsmc_d[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:0] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(data_ne) t w(ne) ai14990 fsmc_nadv (1) t v(nadv_ne) t w(nadv) stm32f205xx, stm32f207xx electrical characteristics d o c id 158 18 re v 5 1 0 7 /1 47 figu re 47 . a sy nc hr onou s m u ltiple x e d psram /nor re ad wa ve f o rms t a b l e 66 . a sy nc hr onou s non- m u lt ip le x e d sram/psram/nor write t i m i ng s (1 )(2) 1. c l = 15 pf . 2. based on characterizatio n , not tested in prod uction. symbol p a rame te r m in max u nit t w(n e ) fsmc_ne lo w time 3 t hc lk ? 1 3 t hc lk + 2 n s t v(nw e_ ne) fsmc_nex lo w to fsmc_nwe l o w t hc lk ? 0.5 t hc lk + 1 . 5 n s t w(n w e) fsmc_nwe lo w time t hc lk ? 0.5 t hc lk + 1 . 5 n s t h(n e _n we) fsmc_nw e h i gh to fsmc_n e hi gh hol d time t hc lk ns t v(a_n e ) f s mc_nex lo w to f s mc_a v a lid 7 .5 ns t h(a_ nwe) ad dress hol d time after fsmc_nw e h i gh t hc lk ns t v(bl_ n e) fsmc_nex lo w to fsmc_bl v a l i d 1 .5 n s t h(bl _n we ) fsmc_bl ho ld ti me a f ter fsmc_ n we high t hc lk ? 0.5 n s t v(da t a _n e) fsmc_nex lo w to data v a lid t hc lk + 7 n s t h(d a t a _ n we) data hold time afte r fsmc_nw e hi gh t hc lk ns t v(nad v _ n e) fsmc_nex lo w to fsmc_nad v lo w 5 .5 ns t w(n a d v ) fsmc_nad v lo w tim e t hc lk + 1 . 5 n s nbl data fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_ne) address fsmc_a[25:16] t v(a_ne) fsmc_nwe t v(a_ne) ai14892b address fsmc_nadv t v(nadv_ne) t w(nadv) t su(data_ne) t h(ad_nadv) fsmc_ne fsmc_noe t w(ne) t w(noe) t v(noe_ne) t h(ne_noe) t h(a_noe) t h(bl_noe) t su(data_noe) t h(data_noe) electrical characteristics stm32f205xx, stm32f207xx 108/147 doc id 15818 rev 5 t a b l e 67 . a sy nc hr onou s m u ltiple x e d psram /nor re ad timings (1)( 2) 1. c l = 15 pf . 2. based on characterizatio n , not tested in prod uction. symbol p a ra meter m in ma x u nit t w(n e ) fsmc_ne lo w time 7t hc lk ? 2 7 t hc lk + 2 n s t v(no e_ ne) f s mc_nex lo w to f s mc_no e lo w 3 t hc lk ? 0.5 3 t hc lk + 1. 5 n s t w(n o e) fsmc_n oe lo w ti me 4t hc lk ? 1 4 t hc lk + 2 n s t h(n e _n oe ) fsmc_n oe hig h to fsmc_ n e h i gh ho ld time ?1 n s t v(a_n e ) f s mc_nex lo w to f s mc_a v a lid 0 ns t v(nad v _ n e) f s mc_nex lo w to f s mc_na d v lo w 3 5 ns t w(n a d v ) fsmc_nad v lo w time t hc lk ?1.5 t hc lk + 1. 5 ns t h(ad_nad v) fsmc_ad (address) v a lid hold time after fsmc_nad v high t hc l k ns t h(a_ noe) address hol d ti me a f ter fsmc_noe high t hc l k ns t h(bl _n oe) fsmc_bl h o ld time afte r fsmc_ n oe hi gh 0 n s t v(bl_ n e) fsmc_n ex lo w to fsmc_bl v a lid 0 n s t su(d at a_ ne) data to fsmc_nex high se tu p time 2t hc lk + 24 n s t su(d at a_ no e) data to fsmc_noe h i gh setup time 2t hc lk + 25 n s t h(d a t a _ n e) data hol d time after fsmc_nex hig h 0 n s t h ( da ta _n oe) data hol d time after fsmc_noe h i gh 0 n s stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 109/147 figu re 48 . a sy nc hr onou s m u ltiple x e d psram /nor wr it e wa v e f o rms t a b l e 68 . a sy nc hr onou s m u ltiple x e d psram /nor wr it e timings (1)( 2) 1. c l = 15 pf . 2. based on characterizatio n , not tested in prod uction. sy mbol p a ra meter m in max u nit t w(n e ) fs mc_ne lo w time 5t hc lk ? 1 5 t hc lk + 2 n s t v(nw e_ ne) fs mc_nex lo w to fs mc_nw e lo w 2 t hc lk 2t hc lk + 1 n s t w(n w e) fsmc_ n we lo w time 2t hc lk ? 1 2 t hc lk + 2 n s t h(n e _n we) fsmc_ n we hig h to fsmc _ne high h o ld time t hc lk ? 1 n s t v(a_n e ) fsmc_ n ex l o w to fsmc_ a v a lid 7 n s t v(nad v _ n e) fs mc_nex lo w to fs mc_nad v lo w 3 5 n s t w(n a d v ) fs mc_nad v lo w time t hc lk ? 1 t hc lk + 1 n s t h(ad_nad v) fsmc_ a d (a ddress) v a li d hold time afte r fs mc_nad v high t hc lk ? 3 n s t h(a_ nwe) add r e ss ho ld time after fsmc_ n we hig h 4t hc lk ns t v(bl_ n e) fsmc_ n ex l o w to fsmc_ b l v a lid 1.6 n s t h(bl _n we ) fsmc_ b l hold time after fsmc_nw e hi gh t hc lk ? 1.5 n s t v(da t a _nad v) f s mc_ n ad v hi gh to da ta v a lid t hc lk + 1. 5 n s t h(d a t a _ n we) data ho ld ti me a f ter fsmc_n we high t hc lk ? 5 n s nbl data fsmc_nex fsmc_nbl[1:0] fsmc_ ad[15:0] t v(bl_ne) t h(data_nwe) fsmc_noe address fsmc_a[25:16] t v(a_ne) t w(nwe) fsmc_nwe t v(nwe_ne) t h(ne_nwe) t h(a_nwe) t h(bl_nwe) t v(a_ne) t w(ne) ai14891b address fsmc_nadv t v(nadv_ne) t w(nadv) t v(data_nadv) t h(ad_nadv) electrical characteristics stm32f205xx, stm32f207xx 110/147 doc id 15818 rev 5 sync h r onous wa ve f o rms and timings fig u r e 49 t h r o u gh fig u r e 52 r epr esen t synchr ono us w a v e f o r m s an d ta b l e 7 0 thr o ug h ta b l e 7 2 pr o v id e th e co rr espo ndin g tim i ngs . th e r e sult s sho w n in t hese t a b l es a r e o b t a ine d wit h th e f o llo wing fsmc conf igu r at ion : bur s t a cce s smo d e = fsmc_bur staccessm ode _ena b l e; m e m o r y t y pe = f s m c _m e m or yt yp e_ cra m; wr it ebu r s t = f s m c _w r i te bur s t_ en ab le; clkdivision = 1; (0 is not supp or t ed, see t he stm3 2f2 0 xxx/ 2 1 x xx ref e ren c e man u al) dat ala t ency = 1 f o r nor flash; dat ala te ncy = 0 f o r psram figure 49. synchronous multiplexed nor/psram read timings fsmc_clk fsmc_nex fsmc_nadv fsmc_a[25:16] fsmc_noe fsmc_ad[15:0] ad[15:0] d1 d2 fsmc_nwait (waitcfg = 1b, waitpol + 0b) fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 1 busturn = 0 t d(clkl-nexl) t d(clkh-nexh) t d(clkl-nadvl) t d(clkl-av) t d(clkl-nadvh) t d(clkh-aiv) t d(clkl-noel) t d(clkh-noeh) t d(clkl-adv) t d(clkl-adiv) t su(adv-clkh) t h(clkh-adv) t su(adv-clkh) t h(clkh-adv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14893e stm32f205xx, stm32f207xx electrical characteristics d o c id 158 18 re v 5 1 1 1 /1 47 t a b l e 69 . s y n c h r onous m u ltiple x e d nor/psram rea d timin g s (1) ( 2) 1. c l = 15 pf . 2. based on characterizatio n , not tested in prod uction. symbol p a ra meter m in max u nit t w(c l k) fsmc _clk per iod 2 7 . 7 n s t d(clkl -nexl ) fsm c _clk lo w to fsmc_nex lo w (x = 0. ..2) 1 .5 ns t d(clkh-nexh) fsmc _clk hig h to fsmc _nex h igh (x = 0...2) t hc lk + 2 n s t d(clkl -nad vl ) fsmc _clk lo w to fsmc_nad v l o w 4 n s t d(clkl -nad vh) fsmc _clk lo w to fsmc_nad v h i gh 5 n s t d(clkl -a v) fsmc _clk lo w to fsmc_ax v a li d (x = 16 ...25) 0 n s t d(c l kh -ai v ) fsmc _clk hig h to fsmc _ax i n v a l i d (x = 1 6 ...25) t hc lk + 2 n s t d(c l kl -no e l) fsmc _clk lo w to fsmc_noe l o w t hc lk +1 n s t d ( cl kh- n oeh) fsmc _clk hig h to fsmc _noe hi gh t hc lk + 0. 5 n s t d(c l kl -ad v ) fsmc _clk lo w to fsmc_ad[15:0] v a li d 1 2 n s t d(clkl -adiv) fsmc _clk lo w to fsmc_ad[15:0] in v a lid 0 n s t su(ad v -c lkh ) fsmc _a/d [15: 0 ] v a l id data be f o re fsmc_c lk hi gh 6 n s t h(c l kh -ad v ) fsmc _a/d [15 : 0 ] v a l i d data after fsmc_clk hi gh t hc lk ? 10 n s t su(n w a i t v -c l kh ) fsmc _nw a it v a li d bef o r e fsmc_clk hi gh 8 n s t h(clkh-nw a itv) fsmc _nw a it v a li d after fsmc_ c lk high 2 n s electrical characteristics stm32f205xx, stm32f207xx 112/147 doc id 15818 rev 5 figure 50. synchronous multiplexed psram write timings fsmc_clk fsmc_nex fsmc_nadv fsmc_a[25:16] fsmc_nwe fsmc_ad[15:0] ad[15:0] d1 d2 fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 1 busturn = 0 t d(clkl-nexl) t d(clkh-nexh) t d(clkl-nadvl) t d(clkl-av) t d(clkl-nadvh) t d(clkh-aiv) t d(clkh-nweh) t d(clkl-nwel) t d(clkl-nblh) t d(clkl-adv) t d(clkl-adiv) t d(clkl-data) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14992d t d(clkl-data) fsmc_nbl stm32f205xx, stm32f207xx electrical characteristics d o c id 158 18 re v 5 1 1 3 /1 47 t a b l e 70 . s y n c h r onous m u ltiple x e d psram writ e t i mings (1) ( 2) 1. c l = 15 pf . 2. based on characterizatio n , not tested in prod uction. sy mbol p a rame ter m in max u nit t w(c l k) fsmc_clk pe r i od 27.7 n s t d(clkl -nexl ) fsmc_clk lo w to fsmc_ne x lo w (x = 0 . ..2) 2 n s t d(clkh-nexh) fsmc_clk hi gh to fsmc_nex high (x = 0...2) t hc lk + 2 ns t d(clkl -nad vl ) fsmc_clk lo w to fsmc_nad v lo w 4 n s t d(clkl -nad vh) fsmc_clk lo w to fsmc_nad v high 5 n s t d(clkl -a v) fsmc_clk lo w to fsmc_ax v a li d (x = 1 6 ...25) 0 n s t d(c l kh -ai v ) fsmc_clk hi gh to fsmc_ax i n v a l i d (x = 1 6 ...25 ) t ck + 2 ns t d(c l kl -nwel ) fsmc_clk lo w to fsmc_nw e l o w 1 n s t d ( cl kh- n weh) fsmc_clk hi gh to fsmc_nw e hi gh t hc lk +1 ns t d(c l kl -ad v ) fsmc_clk lo w to fsmc_ad[15 :0 ] v a l i d 1 2 n s t d(clkl -adiv) fsmc_clk lo w to fsmc_ad[15 :0 ] in v a lid 3 n s t d ( cl k l - d at a) fsmc_a/d[1 5:0] v a lid after fsmc_cl k lo w 6 n s t su(n w a i t v -c l kh ) fsmc_nw a it v a l i d bef o r e fsmc_cl k hi gh 7 n s t h(clkh-nw a itv) fsmc_nw a it v a l i d afte r fsmc_ c lk hig h 2 n s t d(clkl -nbl h) fsmc_clk lo w to fsmc_nbl h i gh 1 n s electrical characteristics stm32f205xx, stm32f207xx 114/147 doc id 15818 rev 5 figu re 51 . s y n c h r onous non- m u ltiple x e d nor/psram re ad timings t a b l e 71 . s y n c h r onous non- m u ltiple x e d nor/psram re ad timings (1)( 2) 1. c l = 15 pf . 2. based on characterizatio n , not tested in prod uction. sy mbol p a rame ter m in ma x u nit t w( clk ) fsmc _clk per iod 2 7.7 ns t d(c l kl -ne xl) fsm c _clk lo w to f smc_nex lo w (x = 0. ..2) 1 . 5 ns t d(clkh-nexh) fsmc _clk hig h to fsmc _nex h igh (x = 0...2) t hc l k + 2 n s t d ( cl k l - n ad vl ) fsmc _clk lo w to fsmc_nad v lo w 4 ns t d ( cl k l - n ad vh ) fsmc _clk lo w to fsmc_nad v high 5 ns t d(c l kl -a v ) fsmc _clk lo w to fsmc_ax v a li d (x = 0...2 5 ) 0 ns t d(c l kh -ai v ) fsmc _clk hig h to fsmc _ax i n v a l i d (x = 0 . ..25) t hc l k + 4 n s t d(c l kl -no e l ) fsmc _clk lo w to fsmc_noe l o w t hc lk + 1.5 ns t d ( cl kh- n o e h) fsmc _clk hig h to fsmc _noe hi gh t hc l k + 1.5 ns t su( d v -c l kh ) fsmc _d[15:0] v a lid data bef o r e fsmc _clk high 6 . 5 ns t h(clkh-d v) fsmc _d[15:0] v a lid d a ta after fsmc_ c lk high 7 ns t su( n w a itv - c l kh ) fsmc _nw a it v a li d bef o r e fsmc_smclk hig h 7 ns t h(clkh-nw a i t v) fsmc _nw a it v a li d after fsmc_ c lk high 2 ns fsmc_clk fsmc_nex fsmc_a[25:0] fsmc_noe fsmc_d[15:0] d1 d2 fsmc_nwait (waitcfg = 1b, waitpol + 0b) fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 1 busturn = 0 t d(clkl-nexl) t d(clkh-nexh) t d(clkl-av) t d(clkh-aiv) t d(clkl-noel) t d(clkh-noeh) t su(dv-clkh) t h(clkh-dv) t su(dv-clkh) t h(clkh-dv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14894d fsmc_nadv t d(clkl-nadvl) t d(clkl-nadvh) stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 115/147 figu re 52 . s y n c h r onous non- m u ltiple x e d psram write t i ming s t a b l e 72 . s y n c h r onous non- m u ltiple x e d psram write t i ming s (1 )(2) 1. c l = 15 pf . 2. based on characterizatio n , not tested in prod uction. sym b ol p a ra meter m in max u nit t w(c l k) fsmc_clk pe r i od 27 .7 ns t d(clkl -nexl ) fsmc_clk lo w to fsmc_n ex lo w (x = 0...2) 2 ns t d(clkh-nexh) fsmc_clk hi gh to fsmc_nex high (x = 0...2) t hc lk + 2 ns t d(clkl -nad vl ) fsmc_clk lo w to fsmc_n ad v lo w 4 ns t d(clkl -nad vh) fsmc_clk lo w to fsmc_n ad v high 5 ns t d(clkl -a v) fsmc_clk lo w to fsmc_ax v a l i d (x = 1 6 ...25) 0 ns t d(c l kh -ai v ) fsmc_clk hi gh to fsmc_ax i n v a l i d (x = 1 6 ...25 ) t ck + 2 ns t d(c l kl -nwel ) fsmc_clk lo w to fsmc_n we l o w 1 ns t d ( cl kh- n weh) fsmc_clk hi gh to fsmc_nw e hi gh t hc lk + 1 ns t d ( cl k l - d at a) fsmc_d[15:0] v a li d data afte r fsmc_ clk lo w 6 ns t su(n w a i t v -c l kh ) fsmc_nw a it v a l id bef o r e fsmc_cl k hi gh 7 ns t h(clkh-nw a itv) fsmc_nw a it v a l i d afte r fsmc_ c lk hig h 2 ns t d(clkl -nbl h) fsmc_clk lo w to fsmc_n bl h i gh 1 ns fsmc_clk fsmc_nex fsmc_a[25:0] fsmc_nwe fsmc_d[15:0] d1 d2 fsmc_nwait (waitcfg = 0b, waitpol + 0b) t w(clk) t w(clk) data latency = 1 busturn = 0 t d(clkl-nexl) t d(clkh-nexh) t d(clkl-av) t d(clkh-aiv) t d(clkh-nweh) t d(clkl-nwel) t d(clkl-data) t su(nwaitv-clkh) t h(clkh-nwaitv) ai14993e fsmc_nadv t d(clkl-nadvl) t d(clkl-nadvh) t d(clkl-data) fsmc_nbl t d(clkl-nblh) electrical characteristics stm32f205xx, stm32f207xx 116/147 doc id 15818 rev 5 pc car d /co m pactfla s h cont r o ller wa vef orms an d timings fig u r e 53 t h r o u gh fig u r e 58 r epr esen t synchr ono us w a v e f o r m s an d ta b l e 7 3 pr o v id es th e co rr es po nd in g tim i n g s . t h e r e sult s sh o w n in t h is tab l e are obtained with the f o llo wing fsmc co nf igu r at ion : co m . f s m c _ s et up t i me = 0 x 04 ; com. fsmc_w ait s et up time = 0x07; com. fsmc_ho l dset up time = 0x04; com.fsmc_hizsetuptime = 0x00; a t t . fsmc_se t u p tim e = 0x04 ; a t t . fsmc_w ait s et up time = 0x07; a t t . fsmc_hold s et up time = 0x04; a t t . fsmc_hizse tu ptim e = 0x00 ; i o .f sm c_ set up t ime = 0 x04; i o .f sm c_ w a itse tu ptime = 0x07 ; io .fs m c _ holdsetuptime = 0x04; i o .f sm c_ hizset upt ime = 0 x00; t c l r se tu pt im e = 0 ; t a rset upt ime = 0 ; figu re 53 . p c ca r d /compa ct fla s h co ntr o ller wa v e f o rms f o r c o mmon memor y rea d a cce ss 1. fsmc _nce4_2 remain s high (inactive du rin g 8-bit access. fsmc_nwe t w(noe) fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 (1) fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nce4_1-noe) t su(d-noe) t h(noe-d) t v(ncex-a) t d(nreg-ncex) t d(niord-ncex) t h(ncex-ai) t h(ncex-nreg) t h(ncex-niord) t h(ncex- niowr ) ai14895b stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 117/147 figu re 54 . p c ca r d /compa ct fla s h co ntr o ller wa v e f o rms f o r c o mmon memor y writ e a cce ss t d(nce4_1-nwe) t w(nwe) t h(nwe-d) t v(nce4_1-a) t d(nreg-nce4_1) t d(niord-nce4_1) t h(nce4_1-ai) memxhiz =1 t v(nwe-d) t h(nce4_1-nreg) t h(nce4_1-niord) t h(nce4_1-niowr) ai14896b fsmc_nwe fsmc_n oe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) t d(d-nwe) fsmc_nce4_2 high electrical characteristics stm32f205xx, stm32f207xx 118/147 doc id 15818 rev 5 figu re 55 . p c ca r d /compa ct fla s h co ntr o ller wa v e f o rms f o r a t t r ib ut e memor y rea d a cce ss 1. only data bits 0...7 are read (bits 8...15 are disregarded). t d(nce4_1-noe) t w(noe) t su(d-noe) t h(noe-d) t v(nce4_1-a) t h(nce4_1-ai) t d(nreg-nce4_1) t h(nce4_1-nreg) ai14897b fsmc_nwe fsmc_noe fsmc_d[15:0] (1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(noe-nce4_1) high stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 119/147 figu re 56 . p c ca r d /compa ct fla s h co ntr o ller wa v e f o rms f o r a t t r ib ut e memor y writ e a cce ss 1. only data b i ts 0...7 ar e driven (bits 8...15 rem ains hi- z ). fi gu re 57 . p c ca r d / c ompa ct fla s h co ntr o l l e r wa v e f o rms f o r i / o spa ce re ad ac ces s t w(nwe) t v(nce4_1-a) t d(nreg-nce4_1) t h(nce4_1-ai) t h(nce4_1-nreg) t v(nwe-d) ai14898b fsmc_nwe fsmc_noe fsmc_d[7:0](1) fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t d(nwe-nce4_1) high t d(nce4_1-nwe) t d(niord-nce4_1) t w(niord) t su(d-niord) t d(niord-d) t v(ncex-a) t h(nce4_1-ai) ai14899b fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord electrical characteristics stm32f205xx, stm32f207xx 120/147 doc id 15818 rev 5 fi gu re 58 . p c ca r d / c ompa ctf l a s h co ntr o l l e r wa ve f o rms f o r i / o spac e wr it e ac ces s t d(nce4_1-niowr) t w(niowr) t v(ncex-a) t h(nce4_1-ai) t h(niowr-d) attxhiz =1 t v(niowr-d) ai14900b fsmc_nwe fsmc_noe fsmc_d[15:0] fsmc_a[10:0] fsmc_nce4_2 fsmc_nce4_1 fsmc_nreg fsmc_niowr fsmc_niord t a b l e 73. sw it c h i ng c h ar act er is ti cs f o r pc ca r d / c f rea d and w r it e c y c l es (1) ( 2) sy mbol p a r a meter m in ma x u nit t v(ncex-a) t v(nce4_1-a) fsmc_ ncex l o w (x = 4_ 1/4_2) to fsmc_a y v a li d (y = 0...10 ) fsmc_nce4 _1 lo w (x = 4_1/4_ 2) to fsmc _a y v a lid (y = 0...10) 0 n s t h(n c ex-ai ) t h(n c e4 _1-a i ) fsmc_ ncex h igh (x = 4_1 /4_2 ) to fsmc _ax i n v a l id (x = 0...10 ) fsmc_nce4_ 1 hig h (x = 4_ 1/4 _2) to fsmc_ax in v a lid (x = 0...10 ) 2. 5 n s t d(n r eg -n cex) t d(n r eg -n ce4 _1) fsmc_ ncex l o w to fsmc_ nreg v a lid fsmc_ nce4_1 lo w to fsmc_nr e g v a li d 5 n s t h(n c ex-n re g) t h(n c e4 _1-n r e g ) fsmc_ ncex hi gh to fsmc_ nreg in v a lid fsmc _nce4_ 1 hi gh to fsmc_nreg in v a l i d t hc lk + 3 ns t d(n c e4 _1-n o e) fsmc_ nce4_1 lo w to fsmc_ n oe lo w 5 t hc l k + 2 n s t w(n o e ) fsmc_ noe lo w width 8 t hc lk ?1.5 8 t hc l k + 1 n s t d(n o e- nc e4_1 fsmc_ n oe hig h to fsmc _nce4_ 1 high 5 t hc lk + 2 n s t su(d -noe) fsmc_ d [1 5:0] v a lid da ta b e f o re fsmc_ n oe hi gh 2 5 ns t h(n o e- d) fsmc_ d [1 5:0] v a lid da ta a f ter fsmc_noe high 1 5 ns t w(n w e) fsmc_ nwe lo w width 8 t hc lk ? 1 8 t hc l k + 2 n s t d(n w e - nc e4_ 1 ) f s mc _n w e h i gh t o fsm c _n c e 4 _ 1 hi g h 5t hc lk + 2 n s t d(n c e4 _1-n w e) fsmc_ nce4_1 lo w to fsmc_ n we lo w 5 t hc l k + 1.5 ns t v(nwe-d ) fsmc_ n we lo w to fsmc_d[15:0] v a li d 0 ns t h(n w e - d) fsmc_ n we hig h to fsmc_ d [15:0] i n v a l i d 1 1t hc lk ns t d(d - nwe) fsmc_ d [1 5:0] v a lid be f o re fsmc_ n we hig h 1 3 t hc lk ns stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 121/147 nand contr o ller wa vef o rms and timings fig u r e 59 t h r o u gh fig u r e 62 r epr esen t synchr ono us w a v e f o r m s an d ta b l e 7 4 pr o vid es th e co rr es po nd in g tim i ng s . t h e r e sult s sh o w n in t h is tab l e are obtained with the f o llo wing fsmc co nf igu r at ion : co m . f s m c _ s et up t i me = 0 x01 ; com. fsmc_w ait s et up time = 0x03; com. fsmc_ho l dset up time = 0x02; com.fsmc_hizsetuptime = 0x01; a t t . fsmc_se t u p tim e = 0x01 ; a t t . fsmc_w ait s et up time = 0x03; a t t . fsmc_hold s et up time = 0x02; a t t . fsmc_hizse tu ptim e = 0x01 ; ba nk = fs mc _ba n k_n and; me mor y dat a wid t h = fsmc_m emo r ydat awidt h _ 16b ; ecc = fs mc _ec c _e na b l e ; eccp ag esiz e = fsmc_eccp a g e siz e _51 2byte s ; t c l r se tu pt im e = 0 ; t a rset upt ime = 0 ; t w(n i o w r) fsmc_ n io wr lo w width 8 t hc lk + 3 n s t v(ni o w r - d) fsmc_ n io w r lo w to fsmc_d[15:0] v a li d 5 t hc l k +1 n s t h ( nio w r - d) f s mc _n i o wr h i gh to fs mc _d [ 1 5 : 0 ] i n v a l i d 11 t hc lk ns t d ( nc e4_ 1 - nio w r) fsmc_ nce4_1 lo w to fsmc_ n io wr v a li d 5 t hc l k + 3ns ns t h(n c ex-n i o wr) t h ( nc e4_ 1 - nio w r) fsmc_ ncex h i gh to fsmc_n io w r in v a l i d fsmc_ nce4_1 h i gh to fsmc_n io w r i n v a l i d 5t hc lk ? 5 n s t d ( ni ord - nc ex ) t d ( ni ord - nc e4_ 1 ) fsmc_ ncex l o w to fsmc_ n iord v a l i d fsmc_ nce4_1 lo w to fsmc_niord v a li d 5t hc l k + 2.5 ns t h ( nc ex - n io rd ) t h ( nc e4_ 1 - nio rd) fsmc_ ncex h i gh to fsmc_n iord in v a lid fsmc_ nce4_1 h i gh to fsmc_n iord in v a lid 5t hc lk ? 5 n s t su(d -niord ) fsmc_ d [1 5:0] v a lid be f o re fsmc_ n iord hig h 4 . 5 ns t d ( ni ord - d) fsmc_ d [1 5:0] v a lid after fsmc_nior d h i gh 9 ns t w(n i o r d) fsmc_ niord lo w wid th 8 t hc lk + 2 n s 1. c l = 15 pf . 2. based on characterization, not tested in prod uction. t a b l e 73. sw it c h i ng c h ar act er is ti cs f o r pc ca r d / c f rea d and w r it e c y c l es (1) ( 2) (co n ti n u e d ) sy mbol p a r a meter m in ma x u nit electrical characteristics stm32f205xx, stm32f207xx 122/147 doc id 15818 rev 5 figure 59. nand contr o ller wa vef o rms f o r read access figure 60. nand contr o ller wa vef o rms f o r write access figure 61. nand controller waveforms for common memo ry read access fsmc_nwe fsmc_noe (nre) fsmc_d[15:0] t su(d-noe) t h(noe-d) ai14901b ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-noe) t h(noe-ale) t h(nwe-d) t v(nwe-d) ai14902b fsmc_nwe fsmc_noe (nre) fsmc_d[15:0] ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-nwe) t h(nwe-ale) fsmc_nwe fsmc_n oe fsmc_d[15:0] t w(noe) t su(d-noe) t h(noe-d) ai14912b ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-noe) t h(noe-ale) stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 123/147 figure 62. nand contr o ller wa vef o rms f o r com m on memor y write access 5.3.24 camera interface (dcmi) timing specifications t a b l e 74. s witc hing c h aracteristics f o r nand flash read and write c y c l es (1) 1. c l = 15 pf . sym b ol p a ra meter m in max u nit t d(d - nwe) (2 ) 2. based on characterizatio n , not tested in prod uction. fsmc_d[15 : 0 ] v a l i d bef ore fsmc_nw e h i gh 6 t hc lk + 12 ns t w(n o e) (2) fsmc_noe lo w width 4 t hc lk ? 1. 5 4 t hc lk + 1. 5 n s t su(d -noe) (2 ) fsmc_d[15 : 0 ] v a l i d data be f o re fsmc_n oe hig h 25 ns t h(n o e - d) (2 ) fsmc_d[15 : 0 ] v a lid data after fsmc_ n oe h i gh 7 n s t w(n w e) (2) fsmc_nwe l o w width 4 t hc lk ? 1 4 t hc lk + 2. 5 n s t v(nwe-d ) (2 ) fsmc_nw e lo w to fsmc_ d [15:0] v a lid 0 n s t h(n w e-d) (2 ) fsmc_nw e h igh to fsmc_d [1 5:0 ] in v a li d 1 0t hcl k + 4 n s t d(al e-nwe) (3 ) 3. guarante ed by design, not tested in production . fsmc_ale v a lid bef o re fsmc_nwe lo w 3 t hc lk + 1. 5 n s t h(nwe-ale) (3 ) fsmc_nw e h i gh to fsmc_al e in v a li d 3 t hc lk + 4. 5 ns t d(al e-noe) (3 ) fsmc_ale v a lid bef o re fsmc_noe lo w 3 t hc lk + 2 n s t h(no e - ale) (3 ) fsmc_nw e h i gh to fsmc_al e in v a li d 3 t hc lk + 4. 5 ns t w(nwe) t h(nwe-d) t v(nwe-d) ai14913b fsmc_nwe fsmc_n oe fsmc_d[15:0] t d(d-nwe) ale (fsmc_a17) cle (fsmc_a16) fsmc_ncex low t d(ale-noe) t h(noe-ale) t a b l e 75 . dcmi c h ara c t e ri st ic s symb ol p ar amete r c o n d i ti on s m i n ma x u ni t f r equ ency r a tio dc mi_pixclk/ f hcl k dc mi_pixclk= 48 m h z 2. 5 electrical characteristics stm32f205xx, stm32f207xx 124/147 doc id 15818 rev 5 5.3.25 sd/sdio mmc ca r d host interface (sdio) c haracteristics unle ss ot he rwise sp ecif ied, th e pa r a m e t e rs giv e n in ta b l e 7 6 are der iv e d fr om t e st s p er f o r me d un der amb i ent t emp er at u r e , f pclkx fr eq u e n cy an d v dd su pply v o lt ag e cond itio ns summariz ed in ta b l e 1 0 . ref e r to se ct ion 5 .3 .1 4: i/o p o r t ch ar a cte r i st ics f o r m o r e d e ta ils o n t h e in pu t/ ou tp ut alt e r n at e fu nc tio n c h a r ac te r i stics ( d [7 :0 ], cm d , ck) . figu re 63 . s dio high- spe e d mode figu re 64 . s d def a ult mod e t a b l e 76 . s d / mm c c h a r ac te ri sti c s sy mbo l p a r a meter c on di ti on s m i n max u n i t f pp c l oc k frequency in da ta tr a n sf er mode c l 30 pf 0 4 8 m hz - s dio_ck/f pcl k 2 freque ncy ratio - - 8 /3 - t w(ckh) ck d, cmd (output) d, cmd (input) t c t w(ckl) t ov t oh t isu t ih t f t r ai14887 ck d, cmd (output) t ovd t ohd ai14888 stm32f205xx, stm32f207xx electrical characteristics doc id 15818 rev 5 125/147 5.3.26 r t c c h aracteristics t w(ckl) cl o c k lo w t i me , f pp = 16 mhz c l 30 pf 32 ns t w(ckh ) c l oc k h i gh time , f pp = 16 m h z c l 30 pf 31 t r cloc k r i se tim e c l 30 pf 3 . 5 t f c l oc k f a ll time c l 30 pf 5 cmd , d inputs (r ef e r enced to c k ) t isu input setup time c l 30 pf 2 ns t ih input hold time c l 30 pf 0 c m d , d ou tpu t s (r ef e r e n ce d to ck) in mm c an d sd hs mo de t ov output v a li d time c l 30 pf 6 ns t oh output hol d time c l 30 pf 0.3 c m d , d ou tpu t s (r ef e r e n ced to ck) in sd default mode (1 ) t ov d output v a li d def a u lt time c l 30 pf 7 ns t ohd output hol d d e f a u l t time c l 30 pf 0.5 1. refer to sdio_clkcr , the sdi clo c k co ntrol register to control the ck output. t a b l e 76 . s d / mm c c h a r ac te ri sti c s (c onti n ue d) sy mbo l p a r a meter c on di ti on s m i n max u n i t tab l e 77 . r tc c h arac te ri st ic s s y mb ol p a rameter c on di tio n s mi n max u nit - f pclk1 /r t c clk frequ ency rat i o an y re ad/wr ite o p e r a ti on f r o m /t o an r t c regi ster 4- - package characteristics stm32f205xx, stm32f207xx 126/147 doc id 15818 rev 5 6 p a c k a g e c h ar acter i st ics 6. 1 p a c k a g e mec h anical data i n or de r t o mee t en viro nme n t a l re qu ire m en ts , st of f e rs th ese de vices in dif f er ent g r ad es of ecop a c k ? pa c k age s , d epe nd ing on th eir le v e l of e n vir onm ent a l com p lian c e . eco p a c k ? spe c if icat ion s , g r ade d e f i nit i on s an d pr od uct sta t us a r e a v aila b l e a t : ww w . st.com . ecop a c k ? is an st tr ade mar k . stm32f205xx, stm32f207xx package characteristics d o c id 158 18 re v 5 1 2 7 /1 47 fig u re 6 5 . l qfp6 4 ? 10 x 1 0 mm 6 4 pin lo w- pr ofile quad f l at pa c k a g e out line (1) figure 6 6 . r eco mm e nde d f o otp r in t (1) ( 2) 1. d r awing is no t to scale. 2. d i mensions a r e in millimeters. a a2 a1 c l1 l e e1 d d1 e b ai14398b 48 32 49 64 17 11 6 1.2 0.3 33 10.3 12.7 10.3 0.5 7.8 12.7 ai14909 t a b l e 78. lq fp64 ? 1 0 x 10 mm 64 p i n l o w- pr o f i l e quad f l a t pa c k a g e me c h an ic al d a t a symbol mi lli meter s i n c h es (1 ) min t yp max m in t y p m ax a 1. 60 0 0 .0 6 3 0 a1 0.05 0 0 .1 5 0 0 . 0 020 0.005 9 a2 1.35 0 1 .4 00 1 . 4 5 0 0 .0 531 0.05 51 0.057 1 b 0 .17 0 0.2 2 0 0 .2 7 0 0 . 0 067 0.00 87 0.010 6 c 0 .09 0 0 . 2 0 0 0 .0 035 0.007 9 d 12.00 0 0.47 24 d1 10.00 0 0.39 37 e 12.00 0 0.47 24 e1 10.00 0 0.39 37 e 0.5 00 0.01 97 0 3.5 7 0 3.5 7 l 0 .45 0 0.6 0 0 0 .7 5 0 0 . 0 177 0.02 36 0.029 5 l 1 1.0 0 0 0.03 94 n nu mb er of pi n s 64 1. values in inches a r e conve r ted from mm and rounded to 4 decimal digits. package characteristics stm32f205xx, stm32f207xx 128/147 doc id 15818 rev 5 fi gu re 67 . w lcsp64+2 - 0 . 400 mm pi tc h w a f e r le ve l c h ip siz e pa c k a g e out line 1. drawing is not to scale . " u m p s i d e 3 i d e v i e w $ e t a i l ! 7 a f e r b a c k s i d e ! b a l l l o c a t i o n ! $ e t a i l ! r o t a t e d b y ? # e e e $ ! & 8 ? - % 3 e a t i n g p l a n e ! ! b % e e e ' & e t a b l e 79. wlcsp64+2 - 0 . 400 mm pi tc h w a f e r le ve l c h i p si z e pa c k a g e mec h a n ic al dat a symbol mi lli meter s i n c h es t yp m in max t yp min m ax a 0 .5 70 0.520 0.620 0.022 4 0 .020 5 0 .0 244 a1 0.1 9 0 0 .170 0.210 0.007 5 0 .006 7 0 .0 083 a2 0.3 8 0 0 .350 0.410 0.015 0 0 .013 8 0 .0 161 b 0 .2 70 0.240 0.300 0.010 6 0 .009 4 0 .0 118 d 3 .6 74 3.654 3.694 0.144 6 0 .143 9 0 .1 454 e 4 .0 06 3.986 4.026 0.157 7 0 .156 9 0 .1 585 e 0.4 00 0.015 7 e1 3.2 0 0 0.126 0 f 0.2 37 0.009 3 g 0.4 03 0.015 9 e e e 0 .050 0.00 20 stm32f205xx, stm32f207xx package characteristics d o c id 158 18 re v 5 1 2 9 /1 47 f i gu re 68 . l q f p10 0 , 1 4 x 14 mm 10 0- p i n lo w- p r o f i l e quad f l at pa c k a g e out line (1) figure 6 9 . r eco mm e nde d f o otp r in t (1) ( 2) 1. d r awing is no t to scale. 2. d i mensions a r e in millimeters. d d1 d3 75 51 50 76 100 26 12 5 e3 e1 e e b pin 1 identification seating plane gage plane c a a2 a1 c ccc 0.25 mm 0.10 inch l l1 k c 1l_me 75 51 50 76 0.5 0.3 16.7 14.3 100 26 12.3 25 1.2 16.7 1 ai14906 t a b l e 80. lq pf10 0 ? 14 x 1 4 mm 1 00- pi n l o w - pr of il e qu ad fl at pac k a g e mec h ani c a l da ta symbol millimeter s i nc hes (1 ) min t yp max m in t y p m ax a 1 .6 00 0. 0 6 3 0 a1 0.05 0 0 .15 0 0.00 2 0 0 . 00 59 a2 1.35 0 1 .40 0 1.45 0 0 .05 3 1 0 .05 5 1 0 .05 7 1 b 0 .17 0 0.22 0 0 .27 0 0.00 67 0 . 00 87 0 . 01 06 c 0 .0 90 0 . 2 0 0 0 .0 03 5 0 . 0 07 9 d 1 5. 80 0 1 6. 00 0 1 6. 20 0 0 .6 22 0 0 . 6 29 9 0 . 6 37 8 d1 13 .8 00 14 .0 0 0 14 .2 0 0 0.54 33 0 . 55 12 0 . 55 91 d3 12 .0 0 0 0 . 47 24 e 1 5 . 80 v 1 6. 00 0 1 6. 20 0 0 .6 22 0 0 . 6 29 9 0 . 6 37 8 e1 13 .8 00 14 .0 0 0 14 .2 0 0 0.54 33 0 . 55 12 0 . 55 91 e3 12 .0 0 0 0 . 47 24 e 0 .5 00 0. 0 1 9 7 l 0 .45 0 0.60 0 0 .75 0 0.01 77 0 . 02 36 0 . 02 95 l 1 1.00 0 0 .03 9 4 k 0 3 . 5 7 0 3 . 5 7 ccc 0.08 0 0 .00 3 1 1. values in inches a r e conve r ted from mm and rounded to 4 decimal digits. package characteristics stm32f205xx, stm32f207xx 130/147 doc id 15818 rev 5 f i gu re 70 . l qfp1 44, 20 x 2 0 mm, 14 4-p i n l o w- pr o f i l e quad f l at pa c k a g e out line (1) figur e 71. rec o mmende d f oot print (1) ( 2) 1. drawing is not to scale. 2. dimen s ions are in millimet ers. d1 d3 d e1 e3 e e pin 1 identification 73 72 37 36 109 144 108 1 aa 2 a 1 b c a1 l l1 k seating plane c ccc c 0.25 mm gage plane me_1a 0.5 0.35 19.9 17.85 22.6 1.35 22.6 19.9 a 1 36 37 72 73 108 109 144 t a b l e 81. lq fp14 4, 2 0 x 20 mm, 144 -p in l o w-p r of i l e q u ad f l a t pa c k a g e me c h ani c al d a ta symbol mi lli meter s inc h es (1) min t yp max m in t y p m ax a 1 .600 0.063 0 a1 0.05 0 0 .150 0 . 0 020 0.005 9 a2 1.35 0 1 .4 00 1 . 450 0 . 0 531 0.05 51 0.057 1 b 0 .17 0 0.2 2 0 0 .270 0 . 0 067 0.00 87 0.010 6 c 0 .090 0 . 200 0 . 0 035 0.007 9 d 2 1 . 8 0 0 22.00 0 22.20 0 0 .8 583 0.86 61 0 . 8 7 4 d1 19 .8 0 0 20.00 0 20.20 0 0 .7 795 0.78 74 0.795 3 d3 17.50 0 0 .689 e 2 1 . 8 0 0 22.00 0 22.20 0 0 .8 583 0.86 61 0.874 0 e1 19 .8 0 0 20.00 0 20.20 0 0 .7 795 0.78 74 0.795 3 e3 17.50 0 0 .68 9 0 e 0.5 00 0.01 97 l 0 .45 0 0.6 0 0 0 .750 0 . 0 177 0.02 36 0.029 5 l1 1.0 0 0 0 .03 9 4 k 0 3 . 5 7 0 3 . 5 7 ccc 0 . 08 0 0 .0 03 1 1. values in inches a r e converted from mm and rounded to 4 decimal digits. stm32f205xx, stm32f207xx package characteristics doc id 15818 rev 5 131/147 figu re 72 . l qfp17 6 - lo w pr of ile qua d flat pac k a g e 24 24 1.4 mm, pa c k a g e o u tline 1. drawing is not to scale . ccc c s e a ting pl a ne c aa 2 a1 c 0.25 mm g au ge pl a ne hd d a1 l l1 k 8 9 88 eh e 45 44 e 1 176 pin 1 identific a tion b 1 33 1 3 2 1t_me zd ze t a b l e 82. lq fp17 6 - lo w pr of il e qua d fl at pac k a g e 24 24 1. 4 mm pa c k a g e mec h a n ic al dat a symbol mi lli meter s i n c h es (1 ) min t yp max m in t y p m ax a 1 .60 0 0.063 0 a1 0.05 0 0 .15 0 0.002 0 0 .005 9 a2 1.35 0 1 .45 0 0.0531 0.057 1 b 0 .17 0 0.27 0 0 .0067 0.010 6 c 0 .09 0 0.20 0 0 .0035 0.007 9 d 2 3.9 0 0 2 4 . 1 0 0 0 .9409 0.948 8 e 2 3.9 0 0 2 4 . 1 0 0 0 .9409 0.948 8 e 0 .5 00 0 . 0 197 hd 2 5.9 0 0 26 .1 00 1.0197 1.027 6 he 2 5.9 0 0 26 .1 00 1.0197 1.027 6 l (2 ) 0.45 0 0 .75 0 0.0177 0.029 5 l1 1 . 000 0 . 0 394 zd 1.25 0 0 .0 492 ze 1.25 0 0 .0 492 k0 7 0 7 ccc 0.0 8 0 0 .0 031 1. values in inches a r e conve r ted from mm and rounded to 4 decimal digits. 2. l dimension is measured at gauge plane at 0.2 5 mm above the seating pla ne. package characteristics stm32f205xx, stm32f207xx 132/147 doc id 15818 rev 5 figu re 73 . u fbga17 6+25 - ult r a t h in fine pit c h ball gr id a rra y 10 10 0 . 6 mm , pac k a g e ou tline 1. drawing is not to scale . s e a ting pl a ne c a2 a4 a 3 c ddd a1 a a b e f d f e e r eee m ca b c fff (176 ba ll s ) ? b m ? ? a0e7_me b a ll a1 a 15 1 t a b l e 83. ufbga17 6 +25 - ult r a t h i n fi ne pi t c h bal l gr id a rra y 10 10 0 . 6 mm mec h ani c a l da ta symbol mi lli meter s i n c h es (1 ) min t yp max m in t y p m ax a 0 .46 0 0.53 0 0 .61 0 0.0181 0 . 0 209 0.02 4 0 a1 0.05 0 0 .08 0 0.11 0 0 .0 02 0 . 0 031 0.004 3 a2 0.40 0 0 .45 0 0.50 0 0 .0157 0 . 0 177 0.019 7 a3 0.1 3 0 0 .0 051 a4 0.27 0 0 .32 0 0.37 0 0 .0106 0 . 0 126 0.014 6 b 0 .30 0 0.35 0 0 .40 0 0.0118 0 . 0 138 0.015 7 d 9 .9 50 1 0 .000 10 .0 5 0 0.3740 0 . 3 937 0.395 7 e 9 .95 0 1 0 .000 10 .0 50 0.3740 0 . 3 937 0.39 5 7 e 0 .60 0 0.65 0 0 .70 0 0.0236 0 . 0 256 0.027 6 f 0 .40 0 0.45 0 0 .50 0 0.0157 0 . 0 177 0.019 7 dd d 0 . 12 0 0. 00 4 7 ee e 0 . 15 0 0. 00 5 9 fff 0.0 80 0 . 0 031 1. values in inches a r e converted from mm and rounded to 4 decimal digits. stm32f205xx, stm32f207xx package characteristics doc id 15818 rev 5 133/147 6. 2 thermal c h aracteristi c s th e ma xim u m ch ip-ju n ct ion t e mp er a t u r e , t j max , in deg rees celsius , ma y be calc ulated u s in g th e f o llo wing e qua tio n : t j max = t a max + ( p d ma x x ja ) wh er e: t a ma x is t h e m a xim u m am bien t t e m per a t ure in c, ja is th e pa c k a g e ju nctio n - t o - a m bie n t t h er ma l resist ance , in c/w , p d max is t h e sum of p int m a x and p i/o ma x (p d max = p in t max + p i/o ma x) , p int m a x is th e pr od u ct of i dd an d v dd , e xpressed in w a tts . this is the maxim u m chip int e r nal p o w e r . p i/o ma x r epr esen ts t he ma xim u m po w e r dissipat ion on ou tp ut pins wh er e: p i/o max = (v ol i ol ) + (( v dd ? v oh ) i oh ), ta kin g in to ac co un t th e ac tua l v ol / i ol an d v oh / i oh of t h e i/ os at lo w an d hig h le v e l in t h e application. ref e renc e document jesd 51 -2 in te g r at ed c i rcu i ts the r m a l t e st m e th od en viro n m e n t c o n d it ion s - n a t u r a l con v ection (still air). a v a ilab l e from ww w . jedec.org. t a b l e 84 . p a c k a g e t h er mal c h ara c te ri st ic s symbol p a r a meter v a l ue unit ja the rmal res i sta n ce junction-ambie nt l q fp 6 4 - 10 1 0 mm / 0.5 mm pi tch 45 c/w the rmal res i sta n ce junction-ambie nt w l csp64 + 2 - 0.4 00 mm pi tch 51 the rmal res i sta n ce junction-ambie nt lq fp 10 0 - 14 1 4 mm / 0. 5 mm pi tch 46 the rmal res i sta n ce junction-ambie nt lq fp 14 4 - 20 2 0 mm / 0. 5 mm pi tch 40 the rmal res i sta n ce junction-ambie nt lq fp 17 6 - 24 2 4 mm / 0. 5 mm pi tch 38 the rmal res i sta n ce junction-ambie nt u f bga1 76 - 1 0 10 mm / 0.5 mm pitch 39 part numbering stm32f205xx, stm32f207xx 134/147 doc id 15818 rev 5 7 p a r t n u mbering f o r a list of a v ailab l e op t i ons ( s pee d, p a c k ag e , et c. ) o r f o r fu r t h e r inf o r m at ion o n an y aspe ct of this de vice , please contact y our neares t st sales of fice . t a b l e 85 . o r d e r ing inf o rmat i on sc he me example: stm3 2 f 20 5 r e t 6 xxx de vice famil y stm32 = arm-ba sed 32-bi t microcon trol ler pr oduct type f = ge neral-pu r po se de vice subfa m il y 20 5 = stm3 2f20x, conn ecti vity , usb o t g fs/hs , camer a interf ace 20 7 = stm32 f 20 x, conn ecti vity , usb o t g fs/hs , camera interf ac e , , ether n et pi n co un t r = 64 pin s o r 66 p i ns (1) 1. th e 66 pins is available on wlcsp packa ge only. v = 1 00 pin s z = 14 4 pins i = 17 6 pin s (2) 2. th e lqf p 176 package is not in production. i t is available only for develop ment. fl as h memo r y siz e b = 1 28 kb ytes of flash memor y c = 256 kb ytes of flash memor y e = 5 12 kb ytes of flash memor y f = 76 8 kb yte s of fla sh me mo r y g = 10 24 kb ytes o f flash memor y pa c k a g e t = lq fp h = ufbga y = wl csp t e mpe r ature rang e 6 = in dustr ia l tempe r ature range , ?40 to 85 c . 7 = in dustr ia l tempe r ature range , ?40 to 105 c . op tio n s xxx = p r o g rammed par ts tr = tape a nd reel stm32f205xx, stm32f207xx application block diagrams doc id 15818 rev 5 135/147 appendix a application b l oc k dia g rams a.1 main applications ver s us pac k a g e ta b l e 8 6 giv e s e x a m ple s of co nf igu r at ion s f o r e a ch pa c k a g e . t a b l e 86. ma i n a ppl i cat i ons v e r s us pa c k a g e f o r st m32 f 20 7xx mi cr oc ont r o l l e r s (1) 6 4 pins 100 pins 144 pins 176 pins conf ig 1 conf ig 2 conf ig 3 conf ig 1 conf ig 2 conf ig 3 conf ig 4 conf ig 1 conf ig 2 conf ig 3 conf ig 4 conf ig 1 conf ig 2 usb 1 ot g fs xxxxxx - x x x f s xxxxxxxxxxxx usb 2 hs ul pi --- x --- x x x x o t g f s --- x x x x x f s - - - xxxxxxxxxx eth e r ne t m i i ----- x x xxxx r m i i ---- xxxxxxxxx spi /i2 s2 spi /i2 s3 - x - - xxxxxxxxx sdio sd i o sdio or dcmi sdio or dcmi - sdio or dcmi sdio or dcmi sdio or dcmi x sdio or dcmi x sdioo r dcmi xxx dcmi 8b its da ta - x x xxx 10 bi ts da ta - x x xxx 12 bi ts da ta - x x xxx 14 bi ts da ta ------- x x x x fsmc no r/ ra m mux e d - - - xxxxxxxxxx no r/ ra m - - - xxxxxx na nd - - - x x x* 22 x* 19 xx * 19 x* 22 x* 19 x* 22 x* 22 c f ------- xxxxxx ca n - xx - xxx - - xx - x 1. x* y : f s m c addre s s limited to ?y?. application block diagrams stm32f205xx, stm32f207xx 136/147 doc id 15818 rev 5 a.2 application e x ampl e wi th regulator off figu re 74 . r eg ula t o r b y p ass /r egula t or of f 1. th is mode is a v aila ble on ly on uf bga176 and wlcsp64+2 packag es. figu re 75 . r eg ula t o r b y p ass /r egula t or of f a nd in ter nal res e t of f 1. th is mode is a v aila ble on ly on wlcsp64+2 p ackage. 2 % ' / & & 6 # ! 0 ? a i 6 # ! 0 ? 0 ! . 2 3 4 ! p p l i c a t i o n r e s e t s i g n a l o p t i o n a l 6 6 $ $ t o 6 0 o w e r d o w n r e s e t r i s e n a f t e r 6 # ! 0 ? 6 # ! 0 ? s t a b i l i z a t i o n 2 % ' / & & 6 # ! 0 ? 6 # ! 0 ? 0 ! 6 6 $ $ t o 6 0 o w e r d o w n r e s e t r i s e n b e f o r e 6 # ! 0 ? 6 # ! 0 ? s t a b i l i z a t i o n . 2 3 4 ) 2 2 / & & 6 $ $ 6 $ $ ! p p l i c a t i o n r e s e t s i g n a l o p t i o n a l 6 # ! 0 ? m o n i t o r i n g % x t r e s e t c o n t r o l l e r a c t i v e w h e n 6 # ! 0 ? 6 2 % ' / & & 6 # ! 0 ? a i 6 # ! 0 ? . 2 3 4 6 ) 2 2 / & & 6 $ $ t o 6 6 $ $ 6 6 $ $ 6 $ $ 6 # ! 0 ? m o n i t o r i n g % x t r e s e t c o n t r o l l e r a c t i v e w h e n 6 $ $ 6 a n d 6 # ! 0 ? 6 6 $ $ stm32f205xx, stm32f207xx application block diagrams doc id 15818 rev 5 137/147 a.3 usb o t g full speed (fs) interface sol u tions figu re 76 . u sb o t g fs periphe ral- onl y c onne ct io n figu re 77 . u sb o t g fs host - o n l y co nne ction 1. stmps2141st r /stu lpi01b needed on ly if the application has to support a v bu s powere d device. a basic powe r switch can be used if 5 v are ava i lable on the application boa rd. 3 4 - & x x x 6 t o 6 $ $ 6 o l a t g e r e g u l a t o r 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 ! 0 ! 5 3 " 3 t d " c o n n e c t o r $ - / 3 # ? ) . / 3 # ? / 5 4 a i 3 4 - & x x 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 ! 0 ! 5 3 " 3 t d ! c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r / 3 # ? ) . / 3 # ? / 5 4 a i b 3 4 - 0 3 3 4 2 3 4 5 , 0 ) " c u r r e n t l i m i t e d p o w e r d i s t r i b u t i o n s w i t c h application block diagrams stm32f205xx, stm32f207xx 138/147 doc id 15818 rev 5 figu re 78 . o t g fs c onn ect ion dual- r o le wit h in te rnal phy 1. external vo ltage regulator o n ly needed when build ing a v bus powere d device. 2. stmps2141st r /stu lpi01b needed on ly if the application has to support a v bu s powere d device. a basic powe r switch can be used if 5 v are ava i lable on the application boa rd. 3. th e same application can b e developpe d using the ot g h s in f s mode to achieve e nhanced performance thanks to the large r x /t x f i fo and to a dedicate d dma co ntroller. a.4 usb o t g high speed (hs) interface solutions figu re 79 . u sb o t g hs pe ripher a l-on l y con n ec tion 3 4 - & x x x 6 $ $ 6 " 5 3 $ 0 6 3 3 0 ! 0 ! 0 ! 5 3 " m i c r o ! " c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r 6 t o 6 $ $ v o l t a g e r e g u l a t o r 6 $ $ ) $ 0 ! / 3 # ? ) . / 3 # ? / 5 4 a i b 3 4 - 0 3 3 4 2 3 4 5 , 0 ) " c u r r e n t l i m i t e d p o w e r d i s t r i b u t i o n s w i t c h 3 4 - & x x x 6 t o 6 $ $ 6 o l a t g e r e g u l a t o r 6 $ $ 6 " 5 3 $ 0 6 3 3 0 " 0 " 0 " 5 3 " 3 t d " c o n n e c t o r $ - / 3 # ? ) . / 3 # ? / 5 4 a i stm32f205xx, stm32f207xx application block diagrams doc id 15818 rev 5 139/147 figu re 80 . u sb o t g hs hos t- onl y conn ect ion 1. stmps2141st r /stu lpi01b needed on ly if the application has to support a v bu s powere d device. a basic powe r switch can be used if 5 v are ava i lable on the application boa rd. figu re 81 . o t g hs co nnec t ion du al -r ol e wi th e xt er n al phy 1. it is po ssib le to u s e mco1 or mc o2 to save a crys t al. it is how ever no t manda to ry to clock the stm32f 20x with a 24 or 26 mhz crystal when using usb hs. t he above figure only shows an example of a possible connection . 3 4 - & x x 3 4 - 0 3 3 4 2 3 4 5 , 0 ) " c u r r e n t l i m i t e d p o w e r d i s t r i b u t i o n s w i t c h 6 $ $ 6 " 5 3 $ 0 6 3 3 5 3 " 3 t d ! c o n n e c t o r $ - ' 0 ) / ) 2 1 ' 0 ) / % . / v e r c u r r e n t 6 0 w r / 3 # ? ) . / 3 # ? / 5 4 a i b 0 " 0 " 0 " $ 0 3 4 - & x x x $ - 6 " 5 3 6 3 3 $ - $ 0 ) $ 5 3 " 5 3 " ( 3 / 4 ' # t r l & 3 0 ( 9 5 , 0 ) ( 3 / 4 ' 0 ( 9 5 , 0 ) ? # , + 5 , 0 ) ? $ ; = 5 , 0 ) ? $ ) 2 5 , 0 ) ? 3 4 0 5 , 0 ) ? . 8 4 n o t c o n n e c t e d c o n n e c t o r - # / o r - # / o r - ( z 8 4 0 , , 8 4 8 ) a i b # a s e o f a n 3 - 3 # w h i c h r e q u i r e d - ( z application block diagrams stm32f205xx, stm32f207xx 140/147 doc id 15818 rev 5 a.5 complete audio pla y er solutions t w o solutions are off e red, illustr a ted in figu re 8 2 an d figu re 8 3 . fig u r e 82 sho w s st or a ge me dia t o au dio d a c/ am plif ier st re amin g using a sof t w ar e code c. th is solu tio n imple m en ts an au dio cr ysta l t o pr o v ide au dio class i 2 s accur a cy on the mast er cloc k (0 .5 % e r r o r m a xim u m, se e th e ser i a l p e r i p her al int e r f a c e se ct ion in t h e re f e re nce ma n ua l f or det ai ls) . figure 82 . c omplet e au dio p l a y e r s o lution 1 fig u r e 83 sho w s st or a ge me dia t o au dio cod e c/ amp lifie r str e a m ing wit h sof synchr oniza tio n of in pu t/ ou tp ut aud io str eam ing u s in g a ha rd w a r e co de c. figu re 83 . c omplet e au dio p l a y e r s o lution 2 cortex-m 3 core u p to 120 mhz otg (ho s t mode) + phy s pi s pi gpio i2 s xtal 25 mhz or 14.7456 mhz u s b m ass - s tor a ge device mmc/ s dc a rd lcd to u ch s creen control bu tton s dac + a u dio a mpli file s y s tem progr a m memory a u dio codec u s er a pplic a tion s tm 3 2f20xxx a i160 3 9 b cortex-m 3 core u p to 120 mhz otg + phy s pi s pi gpio i2 s u s b m ass - s tor a ge device mmc/ s dc a rd lcd to u ch s creen control bu tton s a u dio a mpli file s y s tem progr a m memory a u dio pll +dac u s er a pplic a tion s tm 3 2f20xxx a i16040 b s of s of s ynchroniz a tion of inp u t/o u tp u t au dio s tre a ming xtal 25 mhz or 14.7456 mhz stm32f205xx, stm32f207xx application block diagrams doc id 15818 rev 5 141/147 figu re 84 . a udio pla y er so lut i on usin g pll, plli2s, usb and 1 c r ys ta l figu re 85 . a udio pll ( p l l i2s) pr o v id in g a c c u rat e i2s c l oc k / 4 ' - ( z 0 ( 9 8 4 ! , - ( z o r - ( z 3 4 - & x x a i b ) 3 a c c u r a c y $ ! # ! u d i o a m p l i - # , + o u t 3 # , + - # / - # / 0 , , ) 3 x . 0 , , x . / 3 # $ i v b y - $ i v b y 0 $ i v b y 1 u p t o - ( z # o r t e x - c o r e u p t o - ( z $ i v b y 2 - # , + i n - # / 0 2 % - # / 0 2 % i2 s ctl i2 s _mc k = 256 f s audi o 11 . 2 8 96 mh z f o r 44 . 1 kh z 12 .2 88 0 mh z fo r 4 8 .0 k h z i2 s _m c k plli2 s /m m= 1 , 2, 3 ,..,6 4 1 m hz 19 2 t o 4 3 2 m hz n=192,1 9 4 ,..,4 3 2 i2 s com_ck ph as ec vc o /n /r cl kin ph as e l oc k d et ec t or r= 2 , 3 ,4, 5 ,6 ,7 i2 s d= 2 , 3 , 4 .. 12 9 a i16041 b application block diagrams stm32f205xx, stm32f207xx 142/147 doc id 15818 rev 5 fi gu re 86 . m ast er c l oc k (mck) us ed to d r iv e th e e x te rna l au di o d a c 1. i2s_sck is th e i2s se ria l clo c k to the exter nal au dio d a c (not to be confuse d with i2s_ck). figu re 87 . m ast er c l oc k (mck) not use d to drive t h e e x ter n al audio d a c 1. i2s_sck is the i2s serial clock to the exter nal audio dac (not to be confused with i2s_ck). i2 s _c k i2 s cont rol l e r i2 s _mc k = 256 f s audi o = 1 1 .2 8 96 mh z fo r f s audi o = 4 4 .1 kh z = 12 .2 88 0 m h z f o r f s audi o = 4 8 .0 k h z /(2 x 16) / 8 /i 2 s d f s audi o i2 s _ s ck (1) = i2 s _mck/ 8 for 16- b it s tereo for 16- b it s tereo /(2 x 3 2) /4 for 3 2- b it s tereo f s audio 2, 3 , 4 ,..,129 = i2 s _ m c k /4 f o r 3 2- b it s te re o a i16042 i2 s co m _ c k i2 s controller /( 2 x 1 6 ) /i2 s d f s audio i2 s _ s ck (1) for 16- b it s te re o /( 2 x 3 2) for 3 2- b it s te re o f s aud i o a i16042 stm32f205xx, stm32f207xx revision history doc id 15818 rev 5 143/147 re vision histor y t a b l e 87 . d oc ument re vi si on hi st ory da te re vision cha n g e s 05-j un-2 009 1 i nitial re lease . 09-oct-2009 2 do cu me nt status promot ed from t a rge t specifica t io n to prel iminar y da ta . in t a b l e 5 : stm32f20x pi n a nd ba ll defini t i ons : ? note 4 upd ated ?v dd _sa and v dd _3 pi ns i n v e r t ed ( f i g u r e 1 1: st m3 2f 20 x lq fp1 0 0 pin out , figu re 1 2 : stm3 2f2 0 x lqfp144 p i no ut an d fig u re 13: stm32 f 20 x l q fp176 pi nout corrected accordingly). section 6 .1 : p a c kage mech anica l d a ta chang ed to l q fp w i th n o e xpose d p ad. 0 1 -f eb - 2 01 0 3 lfbga1 44 pac kag e remo v ed. stm32f20 3xx p a r t n u mbers remo v e d . p a r t n u mb ers wi th 1 28 and 2 56 kb yte fla s h d ensitie s ad ded . en cr y p t i o n f e at ur es re mo v e d . pc13 -t amper-r tc rename d to pc13 -r tc_af1 and pi8-t a mper- r t c rena med to pi8-r t c_ af2. revision history stm32f205xx, stm32f207xx 144/147 doc id 15818 rev 5 13-j u l-2 010 4 renamed high-speed sr am, system sram. re mo v e d combin ati on: 128 kbyte s flash memor y in l q fp144 . add ed ufbga176 p a c k age . added n o te 1 re lated to lqfp176 pa c k a ge in ta b l e 2 , figure 1 3 , an d ta b l e 8 5 . add ed inf o r m atio n on ar t accelerator and au dio pll ( p ll i2 s). add ed t a b l e 4 : usar t f eature compar ison . se v e ral upd ates o n t a b l e 5 : stm32f20x pin a nd ba ll defini t i ons and t a b le 6 : alter nate fu nction mapp ing . adc , d a c , o s ci lla tor , r t c_ af , wku p an d vb us signa ls re mo v ed fro m al te r n a t e fun c tio n s a nd mo v e d to th e ?other fu ncti ons? column in t ab l e 5: stm3 2f2 0x pin an d ba ll defin iti ons . traceswo add ed in figure 4 : stm32 f 20 x b l oc k d i ag r a m , ta b l e 5 : stm3 2f2 0 x pin an d b a ll d e fi nition s , and t a b l e 6 : alter n at e function mapp ing . xt al o sci lla tor freque ncy u pda ted o n co v e r page , in fi gure 4 : stm3 2f2 0 x b l oc k dia g ram and in sect ion 2 .2 .1 2: ext e r n al in te rr upt/e v e nt con t ro ller (exti) . up dated list of p e r i ph er a l s used f o r boo t mode i n se ctio n 2 .2.14: bo ot mode s . add ed reg u lator b y pa ss mode i n se ctio n 2 .2.17: v o ltage regu lator , an d se cti o n 5 .3.3: operating con d ition s at po w e r-up / p o w e r-d o wn in regulator b ypass m o de . up dated section 2 .2.18: rea l -ti m e cl oc k (r tc), bac kup sram and ba c k u p registers . add ed note note: in secti o n 2 .2.19: lo w-po w e r modes . add ed spi ti protocol in se ctio n 2 .2.2 8: se r i al pe r i ph er a l in terf ace (spi) . add ed usb o t g_fs f eatures in section 2 .2.33: univ ersal ser i al b u s on -the -go fu ll-spe ed (o tg_ f s) . up dated v cap_1 an d v cap_ 2 ca pacitor v a l ue to 2 . 2 f in fi gure 18 : p o w e r supply s cheme . re mo v e d d a c , modifi ed adc limitation s , and u pdated i/o compe n sation f o r 1.8 to 2 . 1 v r a nge in t a b l e 11: limitation s dep endi ng on the op er a t i ng po w er su ppl y range . add ed v borl , v borm , v bo rh and i ru s h in t a b l e 14: emb edd ed reset an d po w e r co ntro l b l oc k character i stics . re mo v e d ta b l e t ypical curren t consu m p t i on in slee p mo de with fl ash memor y in de ep po w e r do wn mod e . merged typica l a nd maxim u m curren t consu m p t i on secti ons and a dded t a b l e 15: t ypi ca l and maximum curre nt con s u m pti on in ru n mo de , cod e with data pro c e ssing r unn ing from flash , t a b l e 1 6: t y pi ca l a n d m a xi m u m curren t co nsumption in r un mod e , co de w i th da ta processin g r u nni ng from ram , t a b l e 17: t ypi cal and maximum cu rre n t con sumption in sle ep mode , t a b l e 1 8 : t yp i cal an d maxi m u m current co nsumption s in stop mode , t a b l e 1 9 : t y p i cal an d ma xi m u m current co nsumption s i n standb y mod e , a nd t a b le 2 0 : t yp ical an d ma xi m u m current con s u m pti ons in vba t mode . up date t a b l e 2 9: ma i n pl l ch ar a cte r i s tics and a dded sec t ion 5 .3.10: pll spre ad spectr um cloc k gene r a tio n (sscg) ch ar a c ter i sti c s . t a b l e 87 . d oc ument re vi si on hi st ory (co n ti n u e d ) da te re vision cha n g e s stm32f205xx, stm32f207xx revision history doc id 15818 rev 5 145/147 13-j u l- 2 010 4 (contin ued ) add ed note 6 f o r cio in t a b l e 4 0 : i/o static characte r i stics . up dated section 5 .3.16: t i m timer char acter i stics . add ed t nr st _o ut in t a b l e 43: n r st pin ch ar a c ter i sti c s . up dated t a b l e 4 6: i2c character i stics . re mo v e d 8-bit data in an d data out w a v e f o r m s from fi gure 3 6 : ulpi timing d i ag r a m . re mo v e d note rela ted to adc cali br a t io n in ta b l e 6 0 . section 5 .3.18: 12 -bit adc cha r acter i stics : adc char acter i st ics tab l es merged into one sin g le tab l e ; tab l es adc con v ersion time an d ad c a ccu r a cy remo v e d . up dated t a b l e 6 1: d a c ch ar a cter i sti cs . up dated section 5 .3.20 : t e mper a t u r e se nsor characte r i stics a nd section 5 .3 .21 : vba t moni tor i ng cha r acter i stics . up date secti o n 5 .3.24: camer a in terf ace (dcmi) timing sp ecification s . add ed section 5 .3.25: sd/ s dio mmc card host i n terf ace (sdio) char acter i stics , a nd section 5 .3.26: r t c characte r i stics . add ed section 6 .2: t h er ma l char acter i s t ics . u pdated t a b l e 82: lqfp1 76 - l o w profile qu ad fl at p ac kage 24 24 1.4 mm pa c ka ge me ch an i ca l da t a a nd fi gure 7 2 : lqfp17 6 - l o w p r ofi l e qua d fl at pa c k a ge 24 2 4 1.4 mm, p a c kage o u tl ine . ch ange d ta pe and ree l code to tx in t a b l e 8 5: or de r i ng in f o r m a t i o n scheme . add ed t a b l e 8 6 : main ap pli c a t i ons v e rsus pac kag e f o r stm32f20 7xx microcon trol lers . up dated figu res i n ap pen dix a.3: usb o t g full spe ed (fs) interf ace sol u tions an d a.4: usb o t g h i gh spe ed (hs) in te rf ace solutio ns . up dated fi gure 8 4 : a u dio pl a y e r sol u tion usin g pll , plli2s , u s b an d 1 cr ysta l a nd fi gure 8 5 : a u dio pll (pll i2 s) pro viding accur a te i2s cloc k . t a b l e 87 . d oc ument re vi si on hi st ory (co n ti n u e d ) da te re vision cha n g e s revision history stm32f205xx, stm32f207xx 146/147 doc id 15818 rev 5 25- no v-20 10 5 up date i/os in sectio n : f eatures . add ed wlc s p6 6(64+ 2) pac kag e . add ed note 1 rela ted to lqfp1 76 on co v e r pa ge . add ed trade ma r k f o r ar t ac celer a tor . u pdated sect io n 2 .2 .3 : ada p ti v e real -time memor y a c c e l e r a to r ( a r t a c ce lerat o r ? ) . up dated fi gure 5 : mu lti-ahb matr i x . add ed case of bor inactiv a ti on usin g irr o ff on wl csp de vice s in section 2 .2.16: p o w e r supply s u per visor . re w o r k e d secti o n 2 .2.17: v o ltage reg u la tor to cl ar ify re gul ator o f f mode s . rena me d pdr o ff , irr o ff i n th e whol e d o cumen t . add ed section 2 .2.20: vba t ope r a tion . up dated l i n a nd ird a f eatures f o r u a r t 4/5 in t a b l e 4 : u s ar t f eature compar ison . t a b l e 5 : stm32 f 2 0 x p i n and b a ll de fi nition s : modified v dd _3 pin , an d ad ded no te rel a ted to the fsmc_nl pi n; ren a med byp ass-reg regoff , an d add irr o ff p in; re named usar t4 /5 u a r t 4 / 5 . usar t4 pi ns re named u a r t 4. ch ange d v ss _ s a to v ss , and v dd _sa p i n reser v ed f o r futu re use . up dated maxim u m hse cr ystal fre quen cy to 26 mhz. sect ion 5 .2 : absolu te maxi m u m r a t ing s : upd a te d v in mini m u m and maximum v a lue s an d note f o r non -fiv e-v o lt to lerant p i ns in ta b l e 7 : v o l t ag e ch ar a cte r i sti cs . upda te d i inj(pin ) ma xim u m v a lu es a nd rela ted notes in t a b l e 8 : curr ent char acter i st ics . up dated v dd a minim u m v a lue in t a b le 1 0: general op er a t in g con d ition s . add ed note 2 upda te d ma xim u m cpu freq uen cy in t a b l e 11: li mi ta tio n s depe ndi ng on the ope r a tin g po w e r sup p ly r a nge , and ad ded figu re 2 0 : nu mb er of w a i t sta t e s v e rsus fcpu and v dd r a nge . add ed bro w no ut l e v e l 1, 2 , and 3 thresh olds in t a b le 1 4: embe dded reset and p o w e r control b l oc k ch ar a cter i sti cs . ch ange d f osc_ in maxim u m v a lue in t a b l e 24: hse 4-26 mh z o scilla tor char acter i stics . ch ange d f pll _ in maxim u m v a lue in t a b l e 2 9 : ma i n pl l ch ar a cte r i s t i cs , an d upda te d jitte r pa r a me ters in t a b l e 3 0 : pl li 2s (a ud i o pl l) char acter i stics . section 5 . 3 . 1 4: i/ o por t char acter i s t ics : u pda te d v ih and v il in t a b l e 4 0: i/o sta t ic character i stics . add ed note 1 bel o w t a b l e 41: outpu t v o l t a ge characte r i stics . up dated r pd an d r pu par a meter descr iption in t a b l e 51: usb o t g fs dc el ectr ical character i stics . u p dated v ref+ mi nimum v a lue in t a b l e 59: ad c ch ar a c ter i sti c s . up dated t a b l e 6 4: embed ded in te r n al ref e re nce v o ltag e . re mo v e d eth e r n et a nd usb2 f o r 64-pi n de vices in ta b l e 8 6 : m a i n ap plica t i ons v e rsus pac kag e f o r stm32f207 xx microcon tro llers . add ed a.2 : appl ication e xampl e w i th re gula t o r off , remo v e d ?o tg fs con nection wi th e xte r n al phy? fig u re , up dated figure 7 7 , figure 7 8 , an d fig u re 80 to add stu l pi0 1 b. t a b l e 87 . d oc ument re vi si on hi st ory (co n ti n u e d ) da te re vision cha n g e s stm32f205xx, stm32f207xx d o c id 158 18 re v 5 1 4 7 /1 47 pl ea se r e ad c a re fu lly : inf or m at i on i n t hi s d ocumen t i s p r o vi ded so l el y i n co nnecti on wi th st pr oducts. s t mi cr oelect roni cs nv an d i t s su bsi d i a r i e s (? s t ?) re ser ve th e ri ght t o ma ke ch anges , co rr ec ti o ns, mo di f i c at i on s o r i m p r o vem ent s , t o t hi s d ocume nt , and t he pr oducts a nd ser vi c es de scr i bed h e r ei n at any t i me, with ou t no tic e. al l st pr odu ct s a r e s o l d pu rs ua nt to s t ? s t e r m s an d co nd it i o n s of sal e . pur c h a s e r s a r e so le l y r e s pon si bl e fo r t h e c hoi c e , se le ct i o n an d us e o f th e s t pr od uc ts an d s e r v i c e s d e s c r i b e d he re in , and st as s u m es no li a b i l i t y wh at so ev er r e l a t i n g t o t h e cho i ce, se le ct i o n o r u se o f t h e s t pr odu ct s a nd s e r v i c e s de sc ri be d he re in . no l i c e nse , e x p r e s s o r i m pl i e d , b y e s t o p pel or ot he rw is e, t o an y i n t e l l e c t u a l pr op er ty ri gh t s i s gr an te d u nde r t h i s doc ume n t . i f an y pa rt of t h i s do cume n t re f e r s t o an y t h i r d pa rt y p r o duc t s or se rv ic es i t sh al l n o t be d e e m ed a li ce ns e gr an t b y st fo r t h e use of su ch t h i r d par ty pr od uc ts or ser vi c es, or an y in t el l e ct ual p r o per t y c ont a i n ed t her e i n or con si dered as a war r ant y c over i n g t he u se i n a ny manner w hat s oev er o f su ch th i r d p a r t y pr od uct s o r se rv i ces or a n y i n t e ll e c t u a l pr op er t y co nt ai ne d t her ei n . unle ss o t her w ise se t for t h in s t ?s t e rms and co nditions o f sa le s t disc laims an y ex pres s or imp l ied warrant y wit h r espe ct to th e use and/or sa le of st p roduct s in cluding withou t limit ation imp l ied warrant ie s of merch antab il it y, fitne ss f or a parti cul ar p urpos e (and t heir e quivale nts under the laws of any j urisdiction), o r inf rin gement o f any pat e nt, copy right or oth e r in tel lect ual pro pert y rig ht. unle ss e xpre ssly appr oved in writing b y an aut horized st re pres enta tive, st p roduct s are not reco mmended , author iz ed or warrant ed f or us e in milita ry, air cra ft, sp ace, l i f e sa ving, or l i f e su staining appl ications, nor in p roduct s or sy ste ms where failure or malf unction may resu lt in per sonal inj ury , deat h, or s eve re prop erty o r environme ntal d amage. st p roduct s whic h are not s pecified as "automo t ive grade " may only b e used in autom otive app l ications a t user?s own risk. res al e of st pr oduct s wi t h pr ovisions d i f f er ent f r o m t he s t at eme nt s and/ or t echni c al feat ur es s et f o rt h i n this d ocume nt s hal l i mme di at el y v o i d an y wa rr an t y g r a n t e d by st fo r th e s t p r o duc t or se rv i c e de scr i b e d h e r e i n a n d sh al l no t cr ea te or e x t e n d i n any man n e r wha t s o e v er, a n y l i ab il ity of st. st a nd t h e s t lo go a r e tr ad ema r k s or re gi st er ed t r ad emar ks of s t i n va ri ou s co un tr i es. in f o r m at i on i n t h i s do cu men t su pe rs ed es a nd r e p l a c e s al l i n fo rma t i o n pr ev io us ly s u p p l i e d . th e st l o g o is a re gi ste r e d tr ad ema r k o f s t m icr o e l e c t r o n i c s . a ll ot he r n a m es a r e th e pr op er ty of th ei r r e s p e c tiv e ow n e r s . ? 2 0 1 0 s t mic r o e l ec tr on ic s - a l l ri gh ts re se rv ed s t mi cr oe le ctr o n i c s gr ou p of co mp an ie s aus t r al i a - b el gi um - b r a zi l - can ada - ch ina - cz ech rep ubl i c - f i nl and - fr ance - ger m any - ho ng k ong - i ndi a - is rael - i t a l y - ja pa n - m a l a y s i a - ma lt a - mo ro cc o - p h i l i p pi ne s - si ng ap or e - sp ai n - s w ed en - swi t zer l a n d - un it ed ki ngd om - u n i t e d st at e s of amer i c a www .s t.co m |
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